Ben Keller

Ben joined the ASIC & VLSI research group at NVIDIA in 2017 after an internship with the group three years earlier. His research interests include clocking and synchronization, fine-grained adaptive voltage scaling, and improved RTL and VLSI flows for design effort reduction.

Ben received his M.S. and Ph.D. degrees in Electrical Engineering and Computer Sciences from the University of California, Berkeley, in 2015 and 2017, respectively.  He completed his B.S. in Engineering at Harvey Mudd College in 2010.

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