High-speed Low-power On-chip Global Signaling Design Overview

On-chip global signaling in modern SoCs faces significant challenges due to wire pitch scaling and increasing die size. Conventional on-chip synchronous CMOS links have already hit a performance wall in power and latency. Although approaches based on custom low-swing equalized serial-link techniques can yield improvements, strict power/silicon budgets and non-ideal in-situ conditions of large SoCs make their design much more challenging than simply transitioning off-chip signaling technologies to onchip. Therefore, a holistic approach to the on-chip global signaling problem is required. We present analyses and solutions that take into account channel design, low power transceiver circuits, clocking architectures, and power supply considerations.

Authors: 
Rizwan Bashirullah (NVIDIA)
Publication Date: 
Thursday, January 29, 2015
Research Area: