Chia-Tung (Mark) Ho  

 



  ![](/sites/default/files/person/IMG_6784.jpeg)

  

 Chia-Tung Ho received the B.S. and M.S. degrees in electrical engineering and computer science from National Chiao Tung University, Hsinchu, Taiwan, in 2011 and 2013, respectively, and the Ph.D. degree in electrical and computer engineering from the University of California San Diego, USA, in 2022. Chia-Tung has several years of industrial EDA experience under his belt. Before coming to US, he worked for IDM and EDA companies in Taiwan, developing in-house design for manufacturing (DFM) flow at Macronix, and fastSPICE at Mentor Graphics and Synopsys. During his PhD study, he worked with the Design Technology Co-Optimization (DTCO) team in Synopsys as a technical intern from 2019 to 2021, also as an AI resident in X, the Google moonshot factory for 9 months. His research interests include LLM for circuit design, DTCO pathfinding , reinforcement learning for circuit design, machine learning for VLSI design, Power Delivery Network (PDN) optimization, and power grid simulation.



   Research Area(s)

[Algorithms and Numerical Methods](/index.php/research-area/algorithms)

[Artificial Intelligence and Machine Learning ](/index.php/research-area/machine-learning-artificial-intelligence)

[Circuits and VLSI Design](/index.php/research-area/circuits)

[Generative AI](/index.php/research-area/generative-ai)

 

 

  

 Main Field of Interest

[Circuits and VLSI Design](/index.php/research-area/circuits)

 

  

 Google Scholar

[https://scholar.google.com/citations?user=gFmIlekAAAAJ&hl=en](https://scholar.google.com/citations?user=gFmIlekAAAAJ&hl=en)

 

  

 

 

 



 ### Publications

 

### 2025 

[FVDebug: An LLM-Driven Debugging Assistant for Automated Root Cause Analysis of Formal Verification Failures](/publication/2025-09_fvdebug-llm-driven-debugging-assistant-automated-root-cause-analysis-formal)

[Yunsheng Bai](/person/yunsheng-bai), Ghaith Bany Hamad, [Chia-Tung (Mark) Ho](/person/chia-tung-mark-ho), Syed Suhaib, Mark Haoxing Ren













[Marco: Configurable Graph-Based Task Solving and Multi-AI Agents Framework for Hardware Design](/publication/2025-06_marco-configurable-graph-based-task-solving-and-multi-ai-agents-framework)

[Chia-Tung (Mark) Ho](/person/chia-tung-mark-ho), Jing Gong, [Yunsheng Bai](/person/yunsheng-bai), [Chenhui Deng](/person/chenhui-deng), Mark Haoxing Ren, [Brucek Khailany](/person/brucek-khailany)













### 2024 

[DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agent](/index.php/publication/2024-11_drc-coder-automated-drc-checker-code-generation-using-llm-autonomous-agent)

Chen-Chia Chang, [Chia-Tung (Mark) Ho](/index.php/person/chia-tung-mark-ho), Yaguang Li, Yiran Chen, Mark Haoxing Ren



[arXiv](https://arxiv.org/abs/2412.05311)









[VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool](/index.php/publication/2024-08_verilogcoder-autonomous-verilog-coding-agents-graph-based-planning-and-abstract)

[Chia-Tung (Mark) Ho](/index.php/person/chia-tung-mark-ho), Mark Haoxing Ren, [Brucek Khailany](/index.php/person/brucek-khailany)



[arXiv](https://arxiv.org/abs/2408.08927)









[Large Language Model (LLM) for Standard Cell Layout Design Optimization](/index.php/publication/2024-06_large-language-model-llm-standard-cell-layout-design-optimization)

[Chia-Tung (Mark) Ho](/index.php/person/chia-tung-mark-ho), Mark Haoxing Ren



[The First IEEE International Workshop on LLM-Aided Design (LAD'24)](https://arxiv.org/abs/2406.06549)



Best Paper Award





[Novel Transformer Model Based Clustering Method for Standard Cell Design Automation](/publication/2024-03_novel-transformer-model-based-clustering-method-standard-cell-design-automation)

[Chia-Tung (Mark) Ho](/person/chia-tung-mark-ho), Ajay Chandna, David Guan, Alvin Ho, Minsoo Kim, Yaguang Li, Mark Haoxing Ren



[International Symposium on Physical Design 2024](https://dl.acm.org/doi/10.1145/3626184.3633314)



Best Paper Award





### 2023 

[NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model](/index.php/publication/2023-03_nvcell-2-routability-driven-standard-cell-layout-advanced-nodes-lattice-graph)

[Chia-Tung (Mark) Ho](/index.php/person/chia-tung-mark-ho), Alvin Ho, [Matt Fojtik](/index.php/person/matt-fojtik), Minsoo Kim, Shang Wei, Yaguang LI, [Brucek Khailany](/index.php/person/brucek-khailany), Mark Haoxing Ren



[International Symposium on Physical Design 2023](https://ispd.cc/ispd2023/index.php)