Yanqing Zhang  

 



  ![](/sites/default/files/person/Bio.png)

  

 Yanqing joined NVIDIA Research in January of 2014. Prior to joining nVidia, he was a research assistant at the Robust Low Power VLSI research group at the University of Virginia (UVA), where he received his PhD degree in 2013. While at UVA, his research focuses were on low power SoCs, sub-threshold digital circuit design, variation aware timing closure, and variation aware circuit design. Since joining NVIDIA, his research directions include machine learning for EDA applications, digital VLSI methodology, variation resilient digital design, and latch-based timing.



   Research Area(s)

[Circuits and VLSI Design](/index.php/research-area/circuits)

 

 

  

 Main Field of Interest

[Circuits and VLSI Design](/index.php/research-area/circuits)

 

  

 Google Scholar

[https://scholar.google.com/citations?view\_op=list\_works&hl=en&user=CLbekz4AAAAJ…](https://scholar.google.com/citations?view_op=list_works&hl=en&user=CLbekz4AAAAJ&gmla=AJsN-F66U5zUWxVTV4u3oMWZRiZL5_ttSvFtJfshKpiqPFM8kKbIb44-I3BpHRo_CF3io-iq2Tp-tTt9VGoyv35vwgODzOLunmZaG24gOk2lqv4dMJ6vuh0)

 

  

 

 

 



 ### Publications

 

### 2025 

[GEM: GPU-Accelerated Emulator-Inspired RTL Simulation](/publication/2025-06_gem-gpu-accelerated-emulator-inspired-rtl-simulation)

Zizheng Guo, [Yanqing Zhang](/person/yanqing-zhang), Mark Haoxing Ren



[Accepted by Design Automation Conference, 2025](https://62dac.conference-program.com/presentation/?id=RESEARCH396&sess=sess130)



Best Paper Award Nomination at DAC, 2025





### 2024 

[GL0AM: GPU Accelerated Gate Level Logic Simulator](/publication/2024-06_gl0am-gpu-accelerated-gate-level-logic-simulator)

[Yanqing Zhang](/person/yanqing-zhang), Mark Haoxing Ren, [Brucek Khailany](/person/brucek-khailany)













[BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulation](/index.php/publication/2024-03_boolgebra-attributed-graph-learning-boolean-algebraic-manipulation)

Yingjie Li, Anthony Agnesina, [Yanqing Zhang](/index.php/person/yanqing-zhang), Mark Haoxing Ren, Cunxi Yu













### 2022 

[Why are Graph Neural Networks Effective for EDA Problems?](/publication/2022-10_why-are-graph-neural-networks-effective-eda-problems)

Mark Haoxing Ren, Siddhartha Nath, [Yanqing Zhang](/person/yanqing-zhang), Hao Chen, [Mingjie Liu](/person/mingjie-liu)



[2022 International Conference on Computer-Aided Design](https://iccad.com/)









[XT-PRAGGMA: Crosstalk Pessimism Reduction Accessible by GPU Gate-level Simulations and Machine Learning](/publication/2022-09_xt-praggma-crosstalk-pessimism-reduction-accessible-gpu-gate-level-simulations)

Vidya Chhabria, [Ben Keller](/person/ben-keller), [Yanqing Zhang](/person/yanqing-zhang), Sandeep Vollala, Sreedhar Patty, Mark Haoxing Ren, [Brucek Khailany](/person/brucek-khailany)



[MLCAD '22: Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD](https://mlcad-workshop.org/)









[From RTL to CUDA: A GPU Acceleration Flow for RTL Simulation with Batch Stimulus](/index.php/publication/2022-08_rtl-cuda-gpu-acceleration-flow-rtl-simulation-batch-stimulus)

Dian-Lun Lin, Mark Haoxing Ren, [Yanqing Zhang](/index.php/person/yanqing-zhang), [Brucek Khailany](/index.php/person/brucek-khailany), Tsung-Wei Huang



[51st International Conference on Parallel Processing (ICPP '22)](https://icpp22.gitlabpages.inria.fr/)









[GATSPI: GPU Accelerated Gate-Level Simulation for Power Improvement](/index.php/publication/2022-03_gatspi-gpu-accelerated-gate-level-simulation-power-improvement)

[Yanqing Zhang](/index.php/person/yanqing-zhang), Mark Haoxing Ren, Akshay Sridharan, [Brucek Khailany](/index.php/person/brucek-khailany)



[2022 Design Automation Conference](https://www.dac.com)









[Machine Learning and Algorithms: Let Us Team Up for EDA](/index.php/publication/2022-01_machine-learning-and-algorithms-let-us-team-eda)

Mark Haoxing Ren, [Brucek Khailany](/index.php/person/brucek-khailany), [Matt Fojtik](/index.php/person/matt-fojtik), [Yanqing Zhang](/index.php/person/yanqing-zhang)



[IEEE Design & Test](https://ieee-ceda.org/publication/ieee-designtest)









### 2021 

[Simba: scaling deep-learning inference with chiplet-based architecture](/publication/2021-05_simba-scaling-deep-learning-inference-chiplet-based-architecture)

Yakun Sophia Shao, [Jason Clemons](/person/jason-clemons), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Brian Zimmer](/person/brian-zimmer), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Brucek Khailany](/person/brucek-khailany), [Steve Keckler](/person/stephen-keckler)



[Communications of the ACM](https://dl.acm.org/doi/10.1145/3460227)



ACM Research Highlight





[MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification](/publication/2021-02_mavirec-ml-aided-vectored-ir-drop-estimation-and-classification)

Vidya A. Chhabria, [Yanqing Zhang](/person/yanqing-zhang), Mark Haoxing Ren, [Ben Keller](/person/ben-keller), [Brucek Khailany](/person/brucek-khailany), Sachin S. Sapatnekar



[2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)](https://www.date-conference.com/)









### 2020 

[Opportunities for RTL and Gate Level Simulation using GPUs](/publication/2020-11_opportunities-rtl-and-gate-level-simulation-using-gpus)

[Yanqing Zhang](/person/yanqing-zhang), Mark Haoxing Ren, [Brucek Khailany](/person/brucek-khailany)



[IEEE/ACM International Conference on Computer-Aided Design (ICCAD ’20)](https://iccad.com/images/programs/2020_ICCAD_ConferenceProgram.pdf)









[Accelerating Chip Design with Machine Learning](/index.php/publication/2020-09_accelerating-chip-design-machine-learning)

[Brucek Khailany](/index.php/person/brucek-khailany), Mark Haoxing Ren, [Steve Dai](/index.php/person/steve-dai), Saad Godil, [Ben Keller](/index.php/person/ben-keller), Robert Kirby, Alicia Klinefelter, [Rangharajan Venkatesan](/index.php/person/rangharajan-venkatesan), [Yanqing Zhang](/index.php/person/yanqing-zhang), Bryan Catanzaro, [William Dally](/index.php/person/william-dally)



[IEEE Micro](https://ieeexplore.ieee.org/document/9205654)









[GRANNITE: Graph Neural Network Inference for Transferable Power Estimation](/publication/2020-07_grannite-graph-neural-network-inference-transferable-power-estimation)

[Yanqing Zhang](/person/yanqing-zhang), Mark Haoxing Ren, [Brucek Khailany](/person/brucek-khailany)



[Design Automation Conference (DAC) 2020](https://www.dac.com/)









[A 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm](/publication/2020-01_032-128-tops-scalable-multi-chip-module-based-deep-neural-network-inference)

[Brian Zimmer](/person/brian-zimmer), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), Yakun Sophia Shao, [Jason Clemons](/person/jason-clemons), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Steve Keckler](/person/stephen-keckler), [Brucek Khailany](/person/brucek-khailany)



[IEEE Journal of Solid-State Circuits (JSSC)](https://ieeexplore.ieee.org/document/8959403)



JSSC 2020 Best Paper award





[FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning](/index.php/publication/2020-01_fist-feature-importance-sampling-and-tree-based-method-automatic-design-flow)

Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Mark Haoxing Ren, [Yanqing Zhang](/index.php/person/yanqing-zhang), [Brucek Khailany](/index.php/person/brucek-khailany), Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza



[ASP-DAC 2020](https://aspdac2020.github.io/aspdac20/welcome/index.html)









### 2019 

[MAGNet: A Modular Accelerator Generator for Neural Networks](/publication/2019-11_magnet-modular-accelerator-generator-neural-networks)

[Rangharajan Venkatesan](/person/rangharajan-venkatesan), Sophia Shao, Miaorong Wang, [Jason Clemons](/person/jason-clemons), [Steve Dai](/person/steve-dai), [Matt Fojtik](/person/matt-fojtik), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Yanqing Zhang](/person/yanqing-zhang), [Brian Zimmer](/person/brian-zimmer), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Steve Keckler](/person/stephen-keckler), [Brucek Khailany](/person/brucek-khailany)



[International Conference On Computer Aided Design (ICCAD)](https://ieeexplore.ieee.org/document/8942127)









[Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture](/publication/2019-10_simba-scaling-deep-learning-inference-multi-chip-module-based-architecture)

Sophia Shao, [Jason Clemons](/person/jason-clemons), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Brian Zimmer](/person/brian-zimmer), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Brucek Khailany](/person/brucek-khailany), [Steve Keckler](/person/stephen-keckler)



[International Symposium on Microarchitecture (MICRO)](https://dl.acm.org/doi/10.1145/3352460.3358302)



Best Paper award, IEEE Micro Top Picks in Computer Architecture (Honorable Mention)





[A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator Designed with a High-Productivity VLSI Methodology](/publication/2019-08_011-pjop-032-128-tops-scalable-multi-chip-module-based-deep-neural-network)

[Rangharajan Venkatesan](/person/rangharajan-venkatesan), Sophia Shao, [Brian Zimmer](/person/brian-zimmer), [Jason Clemons](/person/jason-clemons), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Steve Keckler](/person/stephen-keckler), [Brucek Khailany](/person/brucek-khailany)



[Hot Chips: A Symposium on High Performance Chips](http://www.hotchips.org/)









[A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm](/publication/2019-06_011-pjop-032-128-tops-scalable-multi-chip-module-based-deep-neural-network)

[Brian Zimmer](/person/brian-zimmer), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), Sophia Shao, [Jason Clemons](/person/jason-clemons), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Steve Keckler](/person/stephen-keckler), [Brucek Khailany](/person/brucek-khailany)



[Symposium on VLSI Circuits](https://ieeexplore.ieee.org/document/8778056)









[PRIMAL: Power Inference using Machine Learning](/publication/2019-06_primal-power-inference-using-machine-learning)

Yuan Zhou, Mark Haoxing Ren, [Yanqing Zhang](/person/yanqing-zhang), [Ben Keller](/person/ben-keller), [Brucek Khailany](/person/brucek-khailany), Zhiru Zhang



[Design Automation Conference (DAC)](https://dac.com/)









### 2018 

[A Modular Digital VLSI Flow for High-Productivity SoC Design](/index.php/publication/2018-06_modular-digital-vlsi-flow-high-productivity-soc-design)

[Brucek Khailany](/index.php/person/brucek-khailany), Evgeni Krimer, [Rangharajan Venkatesan](/index.php/person/rangharajan-venkatesan), [Jason Clemons](/index.php/person/jason-clemons), [Joel Emer](/index.php/person/joel-emer), [Matt Fojtik](/index.php/person/matt-fojtik), Alicia Klinefelter, [Michael Pellauer](/index.php/person/michael-pellauer), [Nathaniel Pinckney](/index.php/person/nathaniel-pinckney), Sophia Shao, Shreesha Srinath, Christopher Torng, Sam (Likun) Xi, [Yanqing Zhang](/index.php/person/yanqing-zhang), [Brian Zimmer](/index.php/person/brian-zimmer)



[Design Automation Conference (DAC)](https://dl.acm.org/doi/10.1145/3195970.3199846)