1. [Publications](/index.php/publications) 2. Designing Efficient Heterogeneous Memory Architectures # Designing Efficient Heterogeneous Memory Architectures ![](/sites/default/files/styles/wide/public/publications/bolotin.ieeemicro2015.png?itok=wPp6wOEw) The authors' model of energy, bandwidth, and latency for DRAM technologies enables exploration of memory hierarchies that combine heterogeneous memory technologies with different attributes. Analysis shows that the gap between on- and off-package DRAM technologies is narrower than that found between cache layers in traditional memory hierarchies. Thus, heterogeneous memory caches must achieve high hit rates or risk degrading both system energy and bandwidth efficiency. ## Authors Evgeny Bolotin (NVIDIA) [David Nellans](/index.php/person/david-nellans) Oreste Villa (NVIDIA) [Mike O'Connor](/index.php/person/mike-o-connor) Alex Ramirez (NVIDIA) [Steve Keckler](/index.php/person/stephen-keckler) [Mike O'Connor](/index.php/person/mike-o-connor) ## Publication Date Saturday, August 15, 2015 ## Published in [IEEE Micro](https://ieeexplore.ieee.org/document/7155441) ## Research Area [Computer Architecture](/index.php/research-area/computer-architecture) ## External Links [Published manuscript](https://ieeexplore.ieee.org/document/7155441) ## Copyright This material is posted here with permission of the IEEE. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to .