1. [Publications](/index.php/publications) 2. A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS # A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS ![](/sites/default/files/styles/wide/public/publications/ISR-SBD.jpg?itok=7vW6csf-) This paper presents a clock-forwarded, Inverter-based Short-Reach Simultaneous Bi-Directional (ISR-SBD) PHY targeted for die-to-die communication over silicon interposer or similar high-density interconnect. Fabricated in a 5nm standard CMOS process, ISR-SBD PHY demonstrates 50.4Gb/s/wire (25.2Gb/s each direction) and 0.297pJ/bit on a 0.75V supply over a 1.2mm on-chip channel. ## Authors [Yoshinori Nishi](/index.php/person/yoshi-nishi) John W. Poulton (NVIDIA) [Xi Chen](/index.php/person/xi-chen) [Sanquan Song](/index.php/person/sanquan-song) [Brian Zimmer](/index.php/person/brian-zimmer) [Walker Turner](/index.php/person/walker-turner) [Stephen Tell](/index.php/person/stephen-tell) [Nikola Nedovic](/index.php/person/nikola-nedovic) [John Wilson](/index.php/person/john-wilson) [William Dally](/index.php/person/william-dally) [Tom Gray](/index.php/person/tom-gray) ## Publication Date Wednesday, June 15, 2022 ## Published in [2022 IEEE SYMPOSIUM ON VLSI TECHNOLOGY & CIRCUITS](https://archive.vlsisymposium.org/22web/about/) ## Research Area [Circuits and VLSI Design](/index.php/research-area/circuits) ## External Links [IEEE Xplore](https://ieeexplore.ieee.org/document/9830174) ## Copyright This material is posted here with permission of the IEEE. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to .