## Circuits and VLSI Design

 ### Associated Publications

 

### 2026 

[Alpha-Vision: A Real-Time Always-on Vision Processor with 787µs Face Detection Latency in <5mW](/index.php/publication/2026-02_alpha-vision-real-time-always-vision-processor-787ms-face-detection-latency)

[Ben Keller](/index.php/person/ben-keller), [Rangharajan Venkatesan](/index.php/person/rangharajan-venkatesan), [Steve Dai](/index.php/person/steve-dai), [Jason Clemons](/index.php/person/jason-clemons), [Matt Fojtik](/index.php/person/matt-fojtik), [Muya Chang](/index.php/person/muya-chang), Thierry Tambe, [Nathaniel Pinckney](/index.php/person/nathaniel-pinckney), [Stephen Tell](/index.php/person/stephen-tell), [Qijing Jenny Huang](/index.php/person/qijing-jenny-huang), [Shalini De Mello](/index.php/person/shalini-de-mello), [Brucek Khailany](/index.php/person/brucek-khailany)



[ISSCC 2026](https://www.isscc.org/)









### 2025 

[FVDebug: An LLM-Driven Debugging Assistant for Automated Root Cause Analysis of Formal Verification Failures](/publication/2025-09_fvdebug-llm-driven-debugging-assistant-automated-root-cause-analysis-formal)

[Yunsheng Bai](/person/yunsheng-bai), Ghaith Bany Hamad, [Chia-Tung (Mark) Ho](/person/chia-tung-mark-ho), Syed Suhaib, Mark Haoxing Ren













[Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems](/publication/2025-06_spec2rtl-agent-automated-hardware-code-generation-complex-specifications-using)

[Zhongzhi Yu](/person/zhongzhi-yu), [Mingjie Liu](/person/mingjie-liu), Michael Zimmer, Yingyan (Celine) Lin, Yong Liu, Mark Haoxing Ren



[IEEE International Conference on LLM-Aided Design, 2025](https://iclad.ai/)









[AssertionForge: Enhancing Formal Verification Assertion Generation with Structured Representation of Specifications and RTL](/publication/2025-06_assertionforge-enhancing-formal-verification-assertion-generation-structured)

[Yunsheng Bai](/person/yunsheng-bai), Ghaith Bany Hamad, Syed Suhaib, Mark Haoxing Ren













[GEM: GPU-Accelerated Emulator-Inspired RTL Simulation](/index.php/publication/2025-06_gem-gpu-accelerated-emulator-inspired-rtl-simulation)

Zizheng Guo, [Yanqing Zhang](/index.php/person/yanqing-zhang), Mark Haoxing Ren



[Accepted by Design Automation Conference, 2025](https://62dac.conference-program.com/presentation/?id=RESEARCH396&sess=sess130)



Best Paper Award Nomination at DAC, 2025





[Marco: Configurable Graph-Based Task Solving and Multi-AI Agents Framework for Hardware Design](/publication/2025-06_marco-configurable-graph-based-task-solving-and-multi-ai-agents-framework)

[Chia-Tung (Mark) Ho](/person/chia-tung-mark-ho), Jing Gong, [Yunsheng Bai](/person/yunsheng-bai), [Chenhui Deng](/person/chenhui-deng), Mark Haoxing Ren, [Brucek Khailany](/person/brucek-khailany)













### 2024 

[DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agent](/publication/2024-11_drc-coder-automated-drc-checker-code-generation-using-llm-autonomous-agent)

Chen-Chia Chang, [Chia-Tung (Mark) Ho](/person/chia-tung-mark-ho), Yaguang Li, Yiran Chen, Mark Haoxing Ren



[arXiv](https://arxiv.org/abs/2412.05311)









[VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool](/index.php/publication/2024-08_verilogcoder-autonomous-verilog-coding-agents-graph-based-planning-and-abstract)

[Chia-Tung (Mark) Ho](/index.php/person/chia-tung-mark-ho), Mark Haoxing Ren, [Brucek Khailany](/index.php/person/brucek-khailany)



[arXiv](https://arxiv.org/abs/2408.08927)









[Large Language Model (LLM) for Standard Cell Layout Design Optimization](/index.php/publication/2024-06_large-language-model-llm-standard-cell-layout-design-optimization)

[Chia-Tung (Mark) Ho](/index.php/person/chia-tung-mark-ho), Mark Haoxing Ren



[The First IEEE International Workshop on LLM-Aided Design (LAD'24)](https://arxiv.org/abs/2406.06549)



Best Paper Award





[GL0AM: GPU Accelerated Gate Level Logic Simulator](/index.php/publication/2024-06_gl0am-gpu-accelerated-gate-level-logic-simulator)

[Yanqing Zhang](/index.php/person/yanqing-zhang), Mark Haoxing Ren, [Brucek Khailany](/index.php/person/brucek-khailany)













[Learning to Compare Hardware Designs for High-Level Synthesis](/publication/2024-05_learning-compare-hardware-designs-high-level-synthesis)

[Yunsheng Bai](/person/yunsheng-bai), Atefeh Sohrabizadeh, Zijian Ding, [Rongjian Liang](/person/rongjian-liang), Weikai Li, Ding Wang, Mark Haoxing Ren, Yizhou Sun, Jason Cong













[A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS](/index.php/publication/2024-04_0190-pjbit-252-gbswire-inverter-based-ac-coupled-transceiver-short-reach-die)

[Yoshinori Nishi](/index.php/person/yoshi-nishi), John W. Poulton, [Xi Chen](/index.php/person/xi-chen), [Sanquan Song](/index.php/person/sanquan-song), [Brian Zimmer](/index.php/person/brian-zimmer), [Walker Turner](/index.php/person/walker-turner), [Stephen Tell](/index.php/person/stephen-tell), [Nikola Nedovic](/index.php/person/nikola-nedovic), [John Wilson](/index.php/person/john-wilson), [William Dally](/index.php/person/william-dally), [Tom Gray](/index.php/person/tom-gray)



[IEEE Journal of Solid-State Circuits (JSSC) (Volume: 59, Issue: 4, April 2024)](https://ieeexplore.ieee.org/document/10185334)









[BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulation](/publication/2024-03_boolgebra-attributed-graph-learning-boolean-algebraic-manipulation)

Yingjie Li, Anthony Agnesina, [Yanqing Zhang](/person/yanqing-zhang), Mark Haoxing Ren, Cunxi Yu













[Novel Transformer Model Based Clustering Method for Standard Cell Design Automation](/publication/2024-03_novel-transformer-model-based-clustering-method-standard-cell-design-automation)

[Chia-Tung (Mark) Ho](/person/chia-tung-mark-ho), Ajay Chandna, David Guan, Alvin Ho, Minsoo Kim, Yaguang Li, Mark Haoxing Ren



[International Symposium on Physical Design 2024](https://dl.acm.org/doi/10.1145/3626184.3633314)



Best Paper Award





[GPU/ML-Enhanced Large Scale Global Routing Contest](/publication/2024-03_gpuml-enhanced-large-scale-global-routing-contest)

[Rongjian Liang](/person/rongjian-liang), Anthony Agnesina, [Wen-Hao Liu](/person/wen-hao-liu), Mark Haoxing Ren



[ISPD 2024](https://ispd.cc/ispd2024/index.php)









[MedPart: A Multi-Level Evolutionary Differentiable Hypergraph Partitioner](/publication/2024-03_medpart-multi-level-evolutionary-differentiable-hypergraph-partitioner)

[Rongjian Liang](/person/rongjian-liang), Anthony Agnesina, Mark Haoxing Ren



[ISPD 2024](https://ispd.cc/ispd2024/index.php)









### 2023 

[CircuitOps: An ML Infrastructure Enabling Generative AI for VLSI Circuit Optimization](/publication/2023-11_circuitops-ml-infrastructure-enabling-generative-ai-vlsi-circuit-optimization)

[Rongjian Liang](/person/rongjian-liang), Anthony Agnesina, Geraldo Pradipta, Vidya A. Chhabria, Mark Haoxing Ren



[2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD) ](https://2023.iccad.com/)









[ChipNeMo: Domain-Adapted LLMs for Chip Design](/index.php/publication/2023-10_chipnemo-domain-adapted-llms-chip-design)

[Mingjie Liu](/index.php/person/mingjie-liu), Teo Ene, Robert Kirby, Chris Cheng, [Nathaniel Pinckney](/index.php/person/nathaniel-pinckney), [Rongjian Liang](/index.php/person/rongjian-liang), Jonah Alben, Himyanshu Anand, Sanmitra Banerjee, Ismet Bayraktaroglu, Bonita Bhaskaran, Bryan Catanzaro, Arjun Chaudhuri, Sharon Clay, Bill Dally, Laura Dang, Parikshit Deshpande, Siddhanth Dhodhi, Sameer Halepete, Eric Hill, Jiashang Hu, Sumit Jain, [Brucek Khailany](/index.php/person/brucek-khailany), George Kokai, Kishor Kunal, Xiaowei Li, Charley Lind, Hao Liu, Stuart Oberman, Sujeet Omar, Sreedhar Pratty, Jonathan Raman, Ambar Sarkar, Zhengjiang Shao, Hanfei Sun, Pratik P Suthar, Varun Tej, [Walker Turner](/index.php/person/walker-turner), Kaizhe Xu, Mark Haoxing Ren













[VerilogEval: Evaluating Large Language Models for Verilog Code Generation](/index.php/publication/2023-09_verilogeval-evaluating-large-language-models-verilog-code-generation)

[Mingjie Liu](/index.php/person/mingjie-liu), [Nathaniel Pinckney](/index.php/person/nathaniel-pinckney), [Brucek Khailany](/index.php/person/brucek-khailany), Mark Haoxing Ren



[2023 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)](https://arxiv.org/abs/2309.07544)









[Late Breaking Results: Test Selection For RTL Coverage By Unsupervised Learning From Fast Functional Simulation](/publication/2023-07_late-breaking-results-test-selection-rtl-coverage-unsupervised-learning-fast)

[Rongjian Liang](/person/rongjian-liang), [Nathaniel Pinckney](/person/nathaniel-pinckney), Yuji Chai, Mark Haoxing Ren, [Brucek Khailany](/person/brucek-khailany)



[60th Design Automation Conference](https://www.dac.com/)









[Efficient Transformer Inference with Statically Structured Sparse Attention](/publication/2023-07_efficient-transformer-inference-statically-structured-sparse-attention)

[Steve Dai](/person/steve-dai), Hasan Genc, [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Brucek Khailany](/person/brucek-khailany)



[2023 60th ACM/IEEE Design Automation Conference (DAC)](https://ieeexplore.ieee.org/xpl/conhome/10247654/proceeding)









[Physics-Informed Optical Kernel Regression Using Complex-valued Neural Fields](/publication/2023-07_physics-informed-optical-kernel-regression-using-complex-valued-neural-fields)

Guojin Chen, Zehua Pei, [Haoyu Yang](/person/haoyu-yang), Yuzhe Ma, Bei Yu, Martin Wong



[60th ACM/IEEE Design Automation Conference](https://arxiv.org/abs/2303.08435)









[A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS](/publication/2023-06_0190-pjbit-252-gbswire-inverter-based-ac-coupled-transceiver-short-reach-die)

[Yoshinori Nishi](/person/yoshi-nishi), John W. Poulton, [Xi Chen](/person/xi-chen), [Sanquan Song](/person/sanquan-song), [Brian Zimmer](/person/brian-zimmer), [Walker Turner](/person/walker-turner), [Stephen Tell](/person/stephen-tell), [Nikola Nedovic](/person/nikola-nedovic), [John Wilson](/person/john-wilson), [William Dally](/person/william-dally), [Tom Gray](/person/tom-gray)



[2023 IEEE SYMPOSIUM ON VLSI TECHNOLOGY & CIRCUITS](https://ieeexplore.ieee.org/abstract/document/10185334)









[A 9.7fJ/Conv.-Step Capacitive Sensor Readout Circuit with Incremental Zoomed Time Domain Quantization](/publication/2023-04_97fjconv-step-capacitive-sensor-readout-circuit-incremental-zoomed-time-domain)

Zilong Shen, Xiyuan Tang, Zhongyi Wu, Haoyang Luo, Zongnan Wang, [Mingjie Liu](/person/mingjie-liu), Xing Zhang, Yuan Wang



[2023 IEEE Custom Integrated Circuits Conference (CICC)](https://ieeexplore.ieee.org/document/10121301)









[A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS](/publication/2023-04_0297-pjbit-504-gbswire-inverter-based-short-reach-simultaneous-bi-directional)

[Yoshinori Nishi](/person/yoshi-nishi), John W. Poulton, [Walker Turner](/person/walker-turner), [Xi Chen](/person/xi-chen), [Sanquan Song](/person/sanquan-song), [Brian Zimmer](/person/brian-zimmer), [Stephen Tell](/person/stephen-tell), [Nikola Nedovic](/person/nikola-nedovic), [John Wilson](/person/john-wilson), [William Dally](/person/william-dally), [Tom Gray](/person/tom-gray)



[IEEE Journal of Solid-State Circuits ( Volume: 58, Issue: 4, April 2023)](https://ieeexplore.ieee.org/document/10011563)









[Reinforcement Learning Guided Detailed Routing for Custom Circuits](/publication/2023-03_reinforcement-learning-guided-detailed-routing-custom-circuits)

Hao Chen, Kai-Chieh Hsu, [Walker Turner](/person/walker-turner), Po-Hsuan Wei, Keren Zhu, David Z. Pan, Mark Haoxing Ren



[International Symposium on Physical Design 2023](https://ispd.cc/ispd2023/index.php)









[AutoDMP: Automated DREAMPlace-based Macro Placement](/index.php/publication/2023-03_autodmp-automated-dreamplace-based-macro-placement)

Anthony Agnesina, Puranjay Rajvanshi, Tian Yang, Geraldo Pradipta, Austin Jiao, [Ben Keller](/index.php/person/ben-keller), [Brucek Khailany](/index.php/person/brucek-khailany), Mark Haoxing Ren



[International Symposium on Physical Design 2023](https://ispd.cc/ispd2023/index.php)









[DREAM-GAN: Advancing DREAMPlace towards Commercial-Quality using Generative Adversarial Learning](/publication/2023-03_dream-gan-advancing-dreamplace-towards-commercial-quality-using-generative)

Yi-Chen Lu, Mark Haoxing Ren, Hao-Hsiang Hsiao, Sung Kyu Lim



[International Symposium on Physical Design 2023](https://ispd.cc/ispd2023/index.php)









[NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model](/publication/2023-03_nvcell-2-routability-driven-standard-cell-layout-advanced-nodes-lattice-graph)

[Chia-Tung (Mark) Ho](/person/chia-tung-mark-ho), Alvin Ho, [Matt Fojtik](/person/matt-fojtik), Minsoo Kim, Shang Wei, Yaguang LI, [Brucek Khailany](/person/brucek-khailany), Mark Haoxing Ren



[International Symposium on Physical Design 2023](https://ispd.cc/ispd2023/index.php)









[On Legalization of Die Bonding Bumps and Pads for 3D ICs](/index.php/publication/2023-03_legalization-die-bonding-bumps-and-pads-3d-ics)

Sai Pentapati, Anthony Agnesina, Moritz Brunion, Yen-Hsiang Huang, Sung Kyu Lim



[International Symposium on Physical Design 2023](https://ispd.cc/ispd2023/index.php)









[Enabling Scalable AI Computational Lithography with Physics-Inspired Models](/publication/2023-02_enabling-scalable-ai-computational-lithography-physics-inspired-models)

[Haoyu Yang](/person/haoyu-yang), Mark Haoxing Ren



[2023 28th Asia and South Pacific Design Automation Conference (ASP-DAC)](https://ieeexplore.ieee.org/document/10044771)









[Beyond CPO: A Motivation and Approach for Bringing Optics onto the Silicon Interposer](/publication/2023-02_beyond-cpo-motivation-and-approach-bringing-optics-silicon-interposer)

[Ben Lee](/person/ben-lee), [Nikola Nedovic](/person/nikola-nedovic), [Trey Greer](/person/trey-greer), [Tom Gray](/person/tom-gray)



[Journal of Lightwave Technology](https://ieeexplore.ieee.org/document/9939069)









[A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm](/publication/2023-01_956-topsw-deep-learning-inference-accelerator-vector-scaled-4-bit-quantization)

[Ben Keller](/person/ben-keller), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Steve Dai](/person/steve-dai), [Stephen Tell](/person/stephen-tell), [Brian Zimmer](/person/brian-zimmer), [Charbel Sakr](/person/charbel-sakr), [William Dally](/person/william-dally), [Tom Gray](/person/tom-gray), [Brucek Khailany](/person/brucek-khailany)



[Journal of Solid-State Circuits](https://ieeexplore.ieee.org/document/10019275)









[BufFormer: A Generative ML Framework for Scalable Buffering](/publication/2023-01_bufformer-generative-ml-framework-scalable-buffering)

[Rongjian Liang](/person/rongjian-liang), Siddhartha Nath, Anand Rajaram, Jiang Hu, Mark Haoxing Ren



[28th Asia and South Pacific Design Automation Conference](https://www.aspdac.com/aspdac2023/cfp/#:~:text=ASP%2DDAC%202023%20is%20the,silicon%20chips%20in%20the%20world.)









### 2022 

[Efficient Arithmetic Block Identification with Graph Learning and Network-flow](/publication/2022-12_efficient-arithmetic-block-identification-graph-learning-and-network-flow)

Ziyi Wang, Zhuolun He, Chen Bai, [Haoyu Yang](/person/haoyu-yang), Bei Yu



[ IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9975800)









[An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design](/publication/2022-12_adversarial-active-sampling-based-data-augmentation-framework-manufacturable)

[Mingjie Liu](/person/mingjie-liu), [Haoyu Yang](/person/haoyu-yang), Zongyi Li, Kumara Sastry, Saumyadip Mukhopadhyay, Selim Dogru, Anima Anandkumar, David Z. Pan, [Brucek Khailany](/person/brucek-khailany), Mark Haoxing Ren



[Workshop on ML for Systems at NeurIPS](http://mlforsystems.org/)









[LNS-Madam: Low-Precision Training in Logarithmic Number System Using Multiplicative Weight Update](/publication/2022-12_lns-madam-low-precision-training-logarithmic-number-system-using-multiplicative)

Jiawei Zhao, [Steve Dai](/person/steve-dai), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Brian Zimmer](/person/brian-zimmer), Mustafa Ali, [Ming-Yu Liu](/person/ming-yu-liu), [Brucek Khailany](/person/brucek-khailany), [William Dally](/person/william-dally), Anima Anandkumar



[IEEE Transactions on Computers (Volume: 71, Issue: 12, 01 December 2022)](https://www.computer.org/csdl/journal/tc)









[TAG: Learning Circuit Spatial Embedding from Layouts](/publication/2022-10_tag-learning-circuit-spatial-embedding-layouts)

Keren Zhu, Hao Chen, [Walker Turner](/person/walker-turner), George F. Kokai, Po-Hsuan Wei, David Z. Pan, Mark Haoxing Ren



[2022 International Conference on Computer-Aided Design](https://iccad.com)









[Why are Graph Neural Networks Effective for EDA Problems?](/publication/2022-10_why-are-graph-neural-networks-effective-eda-problems)

Mark Haoxing Ren, Siddhartha Nath, [Yanqing Zhang](/person/yanqing-zhang), Hao Chen, [Mingjie Liu](/person/mingjie-liu)



[2022 International Conference on Computer-Aided Design](https://iccad.com/)









[TransSizer: A Novel Transformer-Based Fast Gate Sizer](/index.php/publication/2022-10_transsizer-novel-transformer-based-fast-gate-sizer)

Siddhartha Nath, Geraldo Pradipta, Corey Hu, Tian Yang, [Brucek Khailany](/index.php/person/brucek-khailany), Mark Haoxing Ren



[2022 International Conference on Computer-Aided Design](https://iccad.com/)









[Photonic Circuits for Accelerated Computing Systems](/index.php/publication/2022-09_photonic-circuits-accelerated-computing-systems)

[Ben Lee](/index.php/person/ben-lee)



[European Conference on Optical Communication (ECOC), 2022](https://opg.optica.org/abstract.cfm?uri=eceoc-2022-Tu1F.4&origin=search)









[XT-PRAGGMA: Crosstalk Pessimism Reduction Accessible by GPU Gate-level Simulations and Machine Learning](/index.php/publication/2022-09_xt-praggma-crosstalk-pessimism-reduction-accessible-gpu-gate-level-simulations)

Vidya Chhabria, [Ben Keller](/index.php/person/ben-keller), [Yanqing Zhang](/index.php/person/yanqing-zhang), Sandeep Vollala, Sreedhar Patty, Mark Haoxing Ren, [Brucek Khailany](/index.php/person/brucek-khailany)



[MLCAD '22: Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD](https://mlcad-workshop.org/)









[Placement Optimization via PPA-Directed Graph Clustering](/publication/2022-09_placement-optimization-ppa-directed-graph-clustering)

Yi-Chen Lu, Tian Yang, Sung Kyu Lim, Mark Haoxing Ren



[MLCAD '22: Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD](https://mlcad-workshop.org/)









[From RTL to CUDA: A GPU Acceleration Flow for RTL Simulation with Batch Stimulus](/index.php/publication/2022-08_rtl-cuda-gpu-acceleration-flow-rtl-simulation-batch-stimulus)

Dian-Lun Lin, Mark Haoxing Ren, [Yanqing Zhang](/index.php/person/yanqing-zhang), [Brucek Khailany](/index.php/person/brucek-khailany), Tsung-Wei Huang



[51st International Conference on Parallel Processing (ICPP '22)](https://icpp22.gitlabpages.inria.fr/)









[A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS](/index.php/publication/2022-06_0297-pjbit-504-gbswire-inverter-based-short-reach-simultaneous-bidirectional)

[Yoshinori Nishi](/index.php/person/yoshi-nishi), John W. Poulton, [Xi Chen](/index.php/person/xi-chen), [Sanquan Song](/index.php/person/sanquan-song), [Brian Zimmer](/index.php/person/brian-zimmer), [Walker Turner](/index.php/person/walker-turner), [Stephen Tell](/index.php/person/stephen-tell), [Nikola Nedovic](/index.php/person/nikola-nedovic), [John Wilson](/index.php/person/john-wilson), [William Dally](/index.php/person/william-dally), [Tom Gray](/index.php/person/tom-gray)



[2022 IEEE SYMPOSIUM ON VLSI TECHNOLOGY & CIRCUITS](https://archive.vlsisymposium.org/22web/about/)









[A 17–95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm](/publication/2022-06_17-956-topsw-deep-learning-inference-accelerator-vector-scaled-4-bit)

[Ben Keller](/person/ben-keller), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Steve Dai](/person/steve-dai), [Stephen Tell](/person/stephen-tell), [Brian Zimmer](/person/brian-zimmer), [William Dally](/person/william-dally), [Tom Gray](/person/tom-gray), [Brucek Khailany](/person/brucek-khailany)



[2022 Symposium on VLSI Technology & Circuits Digest of Technical Papers](https://www.vlsisymposium.org)









[Saving PAM4 Bus Energy with SMOREs: Sparse Multi-level Opportunistic Restricted Encodings](/index.php/publication/2022-04_saving-pam4-bus-energy-smores-sparse-multi-level-opportunistic-restricted)

[Mike O'Connor](/index.php/person/mike-o-connor), [Donghyuk Lee](/index.php/person/donghyuk-lee), [Niladrish Chatterjee](/index.php/person/niladrish-chatterjee), [Michael B. Sullivan](/index.php/person/mike-sullivan), [Steve Keckler](/index.php/person/stephen-keckler)



[International Symposium on High-Performance Computer Architecture (HPCA)](https://ieeexplore.ieee.org/document/9773229)









[AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies](/index.php/publication/2022-03_autocraft-layout-automation-custom-circuits-advanced-finfet-technologies)

Hao Chen, [Walker Turner](/index.php/person/walker-turner), [Sanquan Song](/index.php/person/sanquan-song), Keren Zhu, George Kokai, [Brian Zimmer](/index.php/person/brian-zimmer), [Tom Gray](/index.php/person/tom-gray), [Brucek Khailany](/index.php/person/brucek-khailany), Mark Haoxing Ren



[International Symposium on Physical Design 2022](https://ispd.cc/ispd2022/slides/ispd2022.html)









[Routability-Aware Placement for Advanced FinFET Analog Circuits with Satisfiability Modulo Theories](/publication/2022-03_routability-aware-placement-advanced-finfet-analog-circuits-satisfiability)

Hao Chen, [Walker Turner](/person/walker-turner), David Z. Pan, Mark Haoxing Ren



[Design, Automation & Test in Europe 2022](https://www.date-conference.com/)









[Generic Lithography Modeling with Dual-band Optics-Inspired Neural Networks](/publication/2022-03_generic-lithography-modeling-dual-band-optics-inspired-neural-networks)

[Haoyu Yang](/person/haoyu-yang), Zongyi Li, Kumara Sastry, Saumyadip Mukhopadhyay, [Mark Kilgard](/person/mark-kilgard), Anima Anandkumar, [Brucek Khailany](/person/brucek-khailany), Vivek Singh, Mark Haoxing Ren



[2022 Design Automation Conference](https://www.dac.com)









[GATSPI: GPU Accelerated Gate-Level Simulation for Power Improvement](/publication/2022-03_gatspi-gpu-accelerated-gate-level-simulation-power-improvement)

[Yanqing Zhang](/person/yanqing-zhang), Mark Haoxing Ren, Akshay Sridharan, [Brucek Khailany](/person/brucek-khailany)



[2022 Design Automation Conference](https://www.dac.com)









[Driving Down Link Energy and Driving Up Link Density in GPU Networks](/index.php/publication/2022-03_driving-down-link-energy-and-driving-link-density-gpu-networks)

[Ben Lee](/index.php/person/ben-lee)



[Optical Fiber Communications (OFC) Conference, 2022](https://ieeexplore.ieee.org/abstract/document/9748251)









[DeePattern: Layout Pattern Generation with Transforming Convolutional Auto-Encoder](/publication/2022-02_deepattern-layout-pattern-generation-transforming-convolutional-auto-encoder)

[Haoyu Yang](/person/haoyu-yang), Shuhe Li, Wen Chen, Piyush Pathak, Frank Gennari, Ya-Chieh Lai, Bei Yu



[IEEE Transactions on Semiconductor Manufacturing](https://ieeexplore.ieee.org/document/9665719)



Best Paper Award





[Machine Learning and Algorithms: Let Us Team Up for EDA](/index.php/publication/2022-01_machine-learning-and-algorithms-let-us-team-eda)

Mark Haoxing Ren, [Brucek Khailany](/index.php/person/brucek-khailany), [Matt Fojtik](/index.php/person/matt-fojtik), [Yanqing Zhang](/index.php/person/yanqing-zhang)



[IEEE Design & Test](https://ieee-ceda.org/publication/ieee-designtest)









### 2021 

[Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers](/publication/2021-12_softermax-hardwaresoftware-co-design-efficient-softmax-transformers)

Jacob R. Stevens, [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Steve Dai](/person/steve-dai), [Brucek Khailany](/person/brucek-khailany), Anand Raghunathan



[Design Automation Conference (DAC) 2021](https://www.dac.com/)









[NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning](/publication/2021-12_nvcell-standard-cell-layout-advanced-technology-nodes-reinforcement-learning)

Mark Haoxing Ren, [Matt Fojtik](/person/matt-fojtik), [Brucek Khailany](/person/brucek-khailany)



Design Automation Conference (DAC) 2021 (Invited special session paper)









[Graph Learning-Based Arithmetic Block Identification](/publication/2021-11_graph-learning-based-arithmetic-block-identification)

Zhuolun He, Ziyi Wang, Chen Bai, [Haoyu Yang](/person/haoyu-yang), Bei Yu



[ IEEE/ACM International Conference on Computer-Aided Design ](https://iccad.com/)









[IPA: Floorplan-Aware SystemC Interconnect Performance Modeling and Generation for HLS-based SoCs](/index.php/publication/2021-11_ipa-floorplan-aware-systemc-interconnect-performance-modeling-and-generation)

[Nathaniel Pinckney](/index.php/person/nathaniel-pinckney), [Rangharajan Venkatesan](/index.php/person/rangharajan-venkatesan), [Ben Keller](/index.php/person/ben-keller), [Brucek Khailany](/index.php/person/brucek-khailany)



[IEEE/ACM International Conference on Computer-Aided Design (ICCAD ’21)](https://iccad.com/)









[Simba: scaling deep-learning inference with chiplet-based architecture](/publication/2021-05_simba-scaling-deep-learning-inference-chiplet-based-architecture)

Yakun Sophia Shao, [Jason Clemons](/person/jason-clemons), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Brian Zimmer](/person/brian-zimmer), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Brucek Khailany](/person/brucek-khailany), [Steve Keckler](/person/stephen-keckler)



[Communications of the ACM](https://dl.acm.org/doi/10.1145/3460227)



ACM Research Highlight





[VS-QUANT: Per-Vector Scaled Quantization for Accurate Low-Precision Neural Network Inference](/publication/2021-04_vs-quant-vector-scaled-quantization-accurate-low-precision-neural-network)

[Steve Dai](/person/steve-dai), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), Mark Haoxing Ren, [Brian Zimmer](/person/brian-zimmer), [William Dally](/person/william-dally), [Brucek Khailany](/person/brucek-khailany)



[MLSys 2021](https://mlsys.org/)









[Fair and Comprehensive Benchmarking of Machine Learning Processing Chips](/index.php/publication/2021-03_fair-and-comprehensive-benchmarking-machine-learning-processing-chips)

Geoffrey W. Burr, SukHwan Lim, Boris Murmann, [Rangharajan Venkatesan](/index.php/person/rangharajan-venkatesan), Marian Verhelst



<https://ieeexplore.ieee.org/document/9367229>









[Verifying High-Level Latency-Insensitive Designs with Formal Model Checking](/index.php/publication/2021-02_verifying-high-level-latency-insensitive-designs-formal-model-checking)

[Steve Dai](/index.php/person/steve-dai), Alicia Klinefelter, Mark Haoxing Ren, [Rangharajan Venkatesan](/index.php/person/rangharajan-venkatesan), [Ben Keller](/index.php/person/ben-keller), [Nathaniel Pinckney](/index.php/person/nathaniel-pinckney), [Brucek Khailany](/index.php/person/brucek-khailany)



[arXiv](https://arxiv.org/abs/2102.06326)









[Ground-Referenced Single-Ended Signaling: Applications for High-Density Short-Haul Communication Systems](/index.php/publication/2021-02_Ground-Referenced-Single-Ended-Signaling%3A)

John Wilson, Walker Turner, John Poulton



Solid-State Circuits Magazine









[Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization](/publication/2021-02_parasitic-aware-analog-circuit-sizing-graph-neural-networks-and-bayesian)

Mingjie Liu, [Walker Turner](/person/walker-turner), George Kokai, David Z. Pan, [Brucek Khailany](/person/brucek-khailany), Mark Haoxing Ren



[2021 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)](https://www.date-conference.com/)









[MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification](/publication/2021-02_mavirec-ml-aided-vectored-ir-drop-estimation-and-classification)

Vidya A. Chhabria, [Yanqing Zhang](/person/yanqing-zhang), Mark Haoxing Ren, [Ben Keller](/person/ben-keller), [Brucek Khailany](/person/brucek-khailany), Sachin S. Sapatnekar



[2021 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)](https://www.date-conference.com/)









[Standard Cell Routing with Reinforcement Learning and Genetic Algorithm in Advanced Technology Nodes](/publication/2021-01_standard-cell-routing-reinforcement-learning-and-genetic-algorithm-advanced)

Mark Haoxing Ren, [Matt Fojtik](/person/matt-fojtik)



[ 26th Asia and South Pacific Design Automation Conference (ASP-DAC) 2021](https://www.aspdac.com/aspdac2021/)









### 2020 

[NVCell: Generate Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning](/publication/2020-12_nvcell-generate-standard-cell-layout-advanced-technology-nodes-reinforcement)

Mark Haoxing Ren, [Matt Fojtik](/person/matt-fojtik), [Brucek Khailany](/person/brucek-khailany)



[ Workshop on ML for Systems at NeurIPS](https://mlforsystems.org/assets/papers/neurips2020/nvcell_ren_2020.pdf)









[How Software Can "Chip In" to the IC Design Process: A Multidisciplinary Approach May Attract New Talent and Accelerate Innovation](/publication/2020-11_how-software-can-chip-ic-design-process-multidisciplinary-approach-may-attract)

Alicia Klinefelter



[IEEE Solid-State Circuits Magazine ](https://ieeexplore.ieee.org/document/9265327)









[Opportunities for RTL and Gate Level Simulation using GPUs](/publication/2020-11_opportunities-rtl-and-gate-level-simulation-using-gpus)

[Yanqing Zhang](/person/yanqing-zhang), Mark Haoxing Ren, [Brucek Khailany](/person/brucek-khailany)



[IEEE/ACM International Conference on Computer-Aided Design (ICCAD ’20)](https://iccad.com/images/programs/2020_ICCAD_ConferenceProgram.pdf)









[Accelerating Chip Design with Machine Learning](/publication/2020-09_accelerating-chip-design-machine-learning)

[Brucek Khailany](/person/brucek-khailany), Mark Haoxing Ren, [Steve Dai](/person/steve-dai), Saad Godil, [Ben Keller](/person/ben-keller), Robert Kirby, Alicia Klinefelter, [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Yanqing Zhang](/person/yanqing-zhang), Bryan Catanzaro, [William Dally](/person/william-dally)



[IEEE Micro](https://ieeexplore.ieee.org/document/9205654)









[ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks](/index.php/publication/2020-07_paragraph-layout-parasitics-and-device-parameter-prediction-using-graph-neural)

Mark Haoxing Ren, George Kokai, [Walker Turner](/index.php/person/walker-turner), Ting-Sheng Ku



[Design Automation Conference (DAC) 2020](https://www.dac.com/)









[GRANNITE: Graph Neural Network Inference for Transferable Power Estimation](/index.php/publication/2020-07_grannite-graph-neural-network-inference-transferable-power-estimation)

[Yanqing Zhang](/index.php/person/yanqing-zhang), Mark Haoxing Ren, [Brucek Khailany](/index.php/person/brucek-khailany)



[Design Automation Conference (DAC) 2020](https://www.dac.com/)









[DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement](/publication/2020-06_dreamplace-deep-learning-toolkit-enabled-gpu-acceleration-modern-vlsi-placement)

Yibo Lin, Zixuan Jiang, Jiaqi Gu, Wuxi Li, Shounak Dhar, Mark Haoxing Ren, [Brucek Khailany](/person/brucek-khailany), David Z. Pan



[IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (…](https://ieeexplore.ieee.org/document/9122053)



2021 IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award





[Reference-Noise Compensation Scheme for Single- Ended Package-to-Package Links](/index.php/publication/2020-02_reference-noise-compensation-scheme-single-ended-package-package-links)

[Xi Chen](/index.php/person/xi-chen), [Nikola Nedovic](/index.php/person/nikola-nedovic), [Stephen Tell](/index.php/person/stephen-tell), [Sudhir Kudva](/index.php/person/sudhir-kudva), [Brian Zimmer](/index.php/person/brian-zimmer), [Trey Greer](/index.php/person/trey-greer), John Poulton, [Sanquan Song](/index.php/person/sanquan-song), [Walker Turner](/index.php/person/walker-turner), [John Wilson](/index.php/person/john-wilson), [Tom Gray](/index.php/person/tom-gray)



[2020 International Solid-State Circuits Conference](http://isscc.org/)









[ABCDPlace: Accelerated Batch-based Concurrent Detailed Placement on Multi-threaded CPUs and GPUs](/publication/2020-02_abcdplace-accelerated-batch-based-concurrent-detailed-placement-multi-threaded)

Yibo Lin, Wuxi Li, Jiaqi Gu, Mark Haoxing Ren, [Brucek Khailany](/person/brucek-khailany), David Z. Pan



[IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (…](https://ieeexplore.ieee.org/document/8982049)









[A 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm](/publication/2020-01_032-128-tops-scalable-multi-chip-module-based-deep-neural-network-inference)

[Brian Zimmer](/person/brian-zimmer), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), Yakun Sophia Shao, [Jason Clemons](/person/jason-clemons), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Steve Keckler](/person/stephen-keckler), [Brucek Khailany](/person/brucek-khailany)



[IEEE Journal of Solid-State Circuits (JSSC)](https://ieeexplore.ieee.org/document/8959403)



JSSC 2020 Best Paper award





[PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network](/publication/2020-01_powernet-transferable-dynamic-ir-drop-estimation-maximum-convolutional-neural)

Zhiyao Xie, Mark Haoxing Ren, [Brucek Khailany](/person/brucek-khailany), Ye Sheng, Santosh Santosh, Jiang Hu, Yiran Chen



[ASP-DAC 2020](https://aspdac2020.github.io/aspdac20/welcome/index.html)









[FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning](/publication/2020-01_fist-feature-importance-sampling-and-tree-based-method-automatic-design-flow)

Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Mark Haoxing Ren, [Yanqing Zhang](/person/yanqing-zhang), [Brucek Khailany](/person/brucek-khailany), Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza



[ASP-DAC 2020](https://aspdac2020.github.io/aspdac20/welcome/index.html)









### 2019 

[MAGNet: A Modular Accelerator Generator for Neural Networks](/publication/2019-11_magnet-modular-accelerator-generator-neural-networks)

[Rangharajan Venkatesan](/person/rangharajan-venkatesan), Sophia Shao, Miaorong Wang, [Jason Clemons](/person/jason-clemons), [Steve Dai](/person/steve-dai), [Matt Fojtik](/person/matt-fojtik), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Yanqing Zhang](/person/yanqing-zhang), [Brian Zimmer](/person/brian-zimmer), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Steve Keckler](/person/stephen-keckler), [Brucek Khailany](/person/brucek-khailany)



[International Conference On Computer Aided Design (ICCAD)](https://ieeexplore.ieee.org/document/8942127)









[Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture](/publication/2019-10_simba-scaling-deep-learning-inference-multi-chip-module-based-architecture)

Sophia Shao, [Jason Clemons](/person/jason-clemons), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Brian Zimmer](/person/brian-zimmer), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Brucek Khailany](/person/brucek-khailany), [Steve Keckler](/person/stephen-keckler)



[International Symposium on Microarchitecture (MICRO)](https://dl.acm.org/doi/10.1145/3352460.3358302)



Best Paper award, IEEE Micro Top Picks in Computer Architecture (Honorable Mention)





[A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator Designed with a High-Productivity VLSI Methodology](/publication/2019-08_011-pjop-032-128-tops-scalable-multi-chip-module-based-deep-neural-network)

[Rangharajan Venkatesan](/person/rangharajan-venkatesan), Sophia Shao, [Brian Zimmer](/person/brian-zimmer), [Jason Clemons](/person/jason-clemons), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Steve Keckler](/person/stephen-keckler), [Brucek Khailany](/person/brucek-khailany)



[Hot Chips: A Symposium on High Performance Chips](http://www.hotchips.org/)









[A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm](/publication/2019-06_011-pjop-032-128-tops-scalable-multi-chip-module-based-deep-neural-network)

[Brian Zimmer](/person/brian-zimmer), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), Sophia Shao, [Jason Clemons](/person/jason-clemons), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Steve Keckler](/person/stephen-keckler), [Brucek Khailany](/person/brucek-khailany)



[Symposium on VLSI Circuits](https://ieeexplore.ieee.org/document/8778056)









[DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement](/publication/2019-06_dreamplace-deep-learning-toolkit-enabled-gpu-acceleration-modern-vlsi-placement)

Yibo Lin, Shounak Dhar, Wuxi Li, Mark Haoxing Ren, [Brucek Khailany](/person/brucek-khailany), David Z. Pan



[Design Automation Conference (DAC) 2019](http://yibolin.com/publications/papers/PLACE_DAC2019_Lin.pdf)



DAC 2019 Best Paper Award





[High Performance Graph Convolutional Networks with Applications in Testability Analysis](/publication/2019-06_high-performance-graph-convolutional-networks-applications-testability-analysis)

Yuzhe Ma, Mark Haoxing Ren, [Brucek Khailany](/person/brucek-khailany), Harbinder Sikka, Lijuan Luo, Karthikeyan Natarajan, Bei Yu



[Design Automation Conference (DAC)](https://dac.com/)









[Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference](/index.php/publication/2019-06_analogmixed-signal-hardware-error-modeling-deep-learning-inference)

Angad S. Rekhi, [Brian Zimmer](/index.php/person/brian-zimmer), [Nikola Nedovic](/index.php/person/nikola-nedovic), Nigxi Liu, [Rangharajan Venkatesan](/index.php/person/rangharajan-venkatesan), Miaorong Wang, [Brucek Khailany](/index.php/person/brucek-khailany), [William Dally](/index.php/person/william-dally), [Tom Gray](/index.php/person/tom-gray)



[Design Automation Conference (DAC)](https://dac.com/)









[PRIMAL: Power Inference using Machine Learning](/publication/2019-06_primal-power-inference-using-machine-learning)

Yuan Zhou, Mark Haoxing Ren, [Yanqing Zhang](/person/yanqing-zhang), [Ben Keller](/person/ben-keller), [Brucek Khailany](/person/brucek-khailany), Zhiru Zhang



[Design Automation Conference (DAC)](https://dac.com/)









[A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET](/publication/2019-05_fine-grained-gals-soc-pausible-adaptive-clocking-16-nm-finfet)

[Matt Fojtik](/person/matt-fojtik), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), [Stephen Tell](/person/stephen-tell), [Brian Zimmer](/person/brian-zimmer), Tezaswi Raja, Kevin Zhou, [William Dally](/person/william-dally), [Brucek Khailany](/person/brucek-khailany)



[ASYNC 2019](http://www.async2019.jp/)



ASYNC 2019 Best Paper Award





[Voltage-Follower Coupling Quadrature Oscillator with Embedded Phase-Interpolator in 16nm FinFET](/publication/2019-04_voltage-follower-coupling-quadrature-oscillator-embedded-phase-interpolator)

[Xi Chen](/person/xi-chen), [Sanquan Song](/person/sanquan-song), John Poulton, [Nikola Nedovic](/person/nikola-nedovic), [Brian Zimmer](/person/brian-zimmer), [Stephen Tell](/person/stephen-tell), [Tom Gray](/person/tom-gray)



[IEEE Custom Integrated Circuits Conference 2019](http://ieee-cicc.org/)









[Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model](/publication/2019-03_routability-driven-macro-placement-embedded-cnn-based-prediction-model)

Yu-Hung Huang, Zhiyao Xie, Guan-Qi Fang, Tao-Chun Yu, Mark Haoxing Ren, Shao-Yun Fang, Yiran Chen, Jiang Hu



[Design, Automation and Test in Europe](http://www.date-conference.com)









[A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator](/index.php/publication/2019-01_117-pjb-25-gbspin-ground-referenced-single-ended-serial-link-and-package)

John Poulton, [John Wilson](/index.php/person/john-wilson), [Walker Turner](/index.php/person/walker-turner), [Brian Zimmer](/index.php/person/brian-zimmer), [Xi Chen](/index.php/person/xi-chen), [Sudhir Kudva](/index.php/person/sudhir-kudva), [Sanquan Song](/index.php/person/sanquan-song), [Stephen Tell](/index.php/person/stephen-tell), [Nikola Nedovic](/index.php/person/nikola-nedovic), Wenxu Zhao, Sunil Sudhakaran, [Tom Gray](/index.php/person/tom-gray), [William Dally](/index.php/person/william-dally)



IEEE JOURNAL OF SOLID-STATE CIRCUITS









### 2018 

[RouteNet: Routability Prediction for Mixed-size Designs using Convolutional Neural Network](/publication/2018-11_routenet-routability-prediction-mixed-size-designs-using-convolutional-neural)

Zhiyao Xie, Yu-Hung Huang, Guan-Qi Fang, Mark Haoxing Ren, Shao-Yun Fang, Yiran Chen, Hu Jiang



[International Conference On Computer Aided Design](http://iccad.com)









[A Modular Digital VLSI Flow for High-Productivity SoC Design](/publication/2018-06_modular-digital-vlsi-flow-high-productivity-soc-design)

[Brucek Khailany](/person/brucek-khailany), Evgeni Krimer, [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Jason Clemons](/person/jason-clemons), [Joel Emer](/person/joel-emer), [Matt Fojtik](/person/matt-fojtik), Alicia Klinefelter, [Michael Pellauer](/person/michael-pellauer), [Nathaniel Pinckney](/person/nathaniel-pinckney), Sophia Shao, Shreesha Srinath, Christopher Torng, Sam (Likun) Xi, [Yanqing Zhang](/person/yanqing-zhang), [Brian Zimmer](/person/brian-zimmer)



[Design Automation Conference (DAC)](https://dl.acm.org/doi/10.1145/3195970.3199846)









[Hardware-Enabled Artificial Intelligence](/index.php/publication/2018-06_hardware-enabled-artificial-intelligence)

[William Dally](/index.php/person/william-dally), [Tom Gray](/index.php/person/tom-gray), John Poulton, [Brucek Khailany](/index.php/person/brucek-khailany), [John Wilson](/index.php/person/john-wilson), [Larry Dennison](/index.php/person/larry-dennison)



Symposia on VLSI Technology and Circuits









[Ground-Referenced Signaling for Intra-Chip and Short-Reach Chip-to-Chip Interconnects](/publication/2018-04_ground-referenced-signaling-intra-chip-and-short-reach-chip-chip-interconnects)

[Walker Turner](/person/walker-turner), John Poulton, [John Wilson](/person/john-wilson), [Xi Chen](/person/xi-chen), [Stephen Tell](/person/stephen-tell), [Matt Fojtik](/person/matt-fojtik), [Trey Greer](/person/trey-greer), [Brian Zimmer](/person/brian-zimmer), [Sanquan Song](/person/sanquan-song), [Nikola Nedovic](/person/nikola-nedovic), [Sudhir Kudva](/person/sudhir-kudva), Sunil Sudhakaran, Rizwan Bashirullah, Wenxu Zhao, [William Dally](/person/william-dally), [Tom Gray](/person/tom-gray)



Custom Integrated Circuits Conference









[A Switching Linear Regulator Based on a Fast-Self-Clocked Comparator with Very Low Probability of Meta-stability and a Parallel Analog Ripple Control Module](/index.php/publication/2018-04_switching-linear-regulator-based-fast-self-clocked-comparator-very-low)

[Sudhir Kudva](/index.php/person/sudhir-kudva), [Sanquan Song](/index.php/person/sanquan-song), John Poulton, [John Wilson](/index.php/person/john-wilson), Wenxu Zhao, [Tom Gray](/index.php/person/tom-gray)



Custom Integrated Circuits Conference









[A 1.17pJ/b 25Gb/s/pin Ground-Referenced Single Ended Serial Link for Off- and On-Package Communication in 16nm CMOS Using a Process- and Temperature-Adaptive Voltage Regulator](/publication/2018-02_117pjb-25gbspin-ground-referenced-single-ended-serial-link-and-package)

[John Wilson](/person/john-wilson), [Walker Turner](/person/walker-turner), John Poulton, [Brian Zimmer](/person/brian-zimmer), [Xi Chen](/person/xi-chen), [Sanquan Song](/person/sanquan-song), [Stephen Tell](/person/stephen-tell), [Nikola Nedovic](/person/nikola-nedovic), Wenxu Zhao, Sunil Sudhakaran, [Tom Gray](/person/tom-gray), [William Dally](/person/william-dally)



ISSCC









### 2017 

[Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology](/index.php/publication/2017-10_ambit-memory-accelerator-bulk-bitwise-operations-using-commodity-dram)

Vivek Seshadri, [Donghyuk Lee](/index.php/person/donghyuk-lee), Thomas Mullins, Hasan Hassan, Amirali Boroumand, Jeremie Kim, Michael A. Kozuch, Onur Mutlu, Phillip B. Gibbons, Todd C. Mowry



[International Symposium on Microarchitecture (MICRO)](https://ieeexplore.ieee.org/document/8686556)









[Xylem: Enhancing Vertical Thermal Conduction in 3D Processor-Memory Stacks](/publication/2017-10_xylem-enhancing-vertical-thermal-conduction-3d-processor-memory-stacks)

Aditya Agrawal, Josep Torrellas, Sachin Idgunji



[International Symposium on Microarchitecture (MICRO)](https://ieeexplore.ieee.org/document/8686607)









[Detecting and Mitigating Data-Dependent DRAM Failures by Exploiting Current Memory Content](/publication/2017-10_detecting-and-mitigating-data-dependent-dram-failures-exploiting-current-memory)

Samira Khan, Chris Wilkerson, Zhe Wang, Alaa R. Alameldeen, [Donghyuk Lee](/person/donghyuk-lee), Onur Mutlu



[International Symposium on Microarchitecture (MICRO)](https://ieeexplore.ieee.org/document/8686523)









### 2016 

[Snatch: Opportunistically Reassigning Power Allocation between Processor and Memory in 3D Stacks](/publication/2016-10_snatch-opportunistically-reassigning-power-allocation-between-processor-and)

Dimitrios Skarlatos, Renji Thomas, Aditya Agrawal, Shibin Qin, Robert Pilawa-Podgurski, Ulya R. Karpuzcu, Radu Teodorescu, Nam Sung Kim, Josep Torrellas



[International Symposium on Microarchitecture (MICRO)](https://ieeexplore.ieee.org/document/7783757)









[Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks](/index.php/publication/2016-05_modeling-and-analysis-power-supply-noise-tolerance-fine-grained-gals-adaptive)

Divya Akella Kamakshi, [Matt Fojtik](/index.php/person/matt-fojtik), [Brucek Khailany](/index.php/person/brucek-khailany), [Sudhir Kudva](/index.php/person/sudhir-kudva), Yaping Zhou, Benton H. Calhoun



[ASYNC 2016](http://www.inf.pucrs.br/async2016/)



ASYNC 2016 Best Paper Award Nominee





[Hybrid Modulation for Near Zero Display Latency](/publication/2016-05_hybrid-modulation-near-zero-display-latency)

[Trey Greer](/person/trey-greer), [Josef Spjut](/person/josef-spjut), [David Luebke](/person/david-luebke), Turner Whitted



[SID](https://sid.onlinelibrary.wiley.com/doi/abs/10.1002/sdtp.10614)









[Current parking regulator for zero droop/overshoot load transient response](/index.php/publication/2016-03_current-parking-regulator-zero-droopovershoot-load-transient-response)

[Sudhir Kudva](/index.php/person/sudhir-kudva), [William Dally](/index.php/person/william-dally), [Trey Greer](/index.php/person/trey-greer), [Tom Gray](/index.php/person/tom-gray)



Applied Power Electronics Conference and Exposition (APEC)









[A 6.5-to-23.3fJ/b/mm Balanced Charge-Recycling Bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with Clock Forwarding and Low-Crosstalk Contraflow Wiring](/index.php/publication/2016-02_65-233fjbmm-balanced-charge-recycling-bus-16nm-finfet-cmos-17-26gbswire-clock)

[John Wilson](/index.php/person/john-wilson), [Matt Fojtik](/index.php/person/matt-fojtik), John Poulton, [Xi Chen](/index.php/person/xi-chen), [Stephen Tell](/index.php/person/stephen-tell), [Trey Greer](/index.php/person/trey-greer), [Tom Gray](/index.php/person/tom-gray), [William Dally](/index.php/person/william-dally)



[International Solid-State Circuits Conference (ISSCC 2016)](http://ieeexplore.ieee.org/document/7417954/)









[A 28nm 2Mbit 6T SRAM with Highly Configurable Write Assist Implementation and Capacitor Based Sense Amplifier Input Offset Compen](/publication/2016-02_28nm-2mbit-6t-sram-highly-configurable-write-assist-implementation-and)

Mahmut Sinangil, John Poulton, [Matt Fojtik](/person/matt-fojtik), [Trey Greer](/person/trey-greer), [Stephen Tell](/person/stephen-tell), Andy Gotterba, Jesse Wang, Jason Golbus, [William Dally](/person/william-dally), [Tom Gray](/person/tom-gray)



Journal of Solid State Circuits









### 2015 

[A Pausible Bisynchronous FIFO for GALS Systems](/publication/2015-05_pausible-bisynchronous-fifo-gals-systems)

Ben Keller, [Matt Fojtik](/person/matt-fojtik), [Brucek Khailany](/person/brucek-khailany)



[ASYNC 2015](http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7152683&tag=1)









[High-speed Low-power On-chip Global Signaling Design Overview](/index.php/publication/2015-01_high-speed-low-power-chip-global-signaling-design-overview)

[Xi Chen](/index.php/person/xi-chen), [John Wilson](/index.php/person/john-wilson), John Poulton, Rizwan Bashirullah, [Tom Gray](/index.php/person/tom-gray)



[DesignCon](http://presentations.designcon.com/events/santa-clara/2015/conference-sessions)









### 2014 

[A Reverse Write Assist Circuit for SRAM Dynamic Write VMIN Tracking using Canary SRAMs](/index.php/publication/2014-03_reverse-write-assist-circuit-sram-dynamic-write-vmin-tracking-using-canary)

Arijit Banerjee, Mahmut Sinangil, John Poulton, [Tom Gray](/index.php/person/tom-gray), Ben Calhoun



 International Symposium on Quality Electronic Design 









### 2013 

[A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications](/index.php/publication/2013-12_054-pjb-20-gbs-ground-referenced-single-ended-short-reach-serial-link-28-nm)

John Poulton, [William Dally](/index.php/person/william-dally), [Xi Chen](/index.php/person/xi-chen), John Eyles, [Trey Greer](/index.php/person/trey-greer), [Stephen Tell](/index.php/person/stephen-tell), [John Wilson](/index.php/person/john-wilson), [Tom Gray](/index.php/person/tom-gray)



[Journal of Solid State Circuits](http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6601723)









[21st Century Digital Design Tools](/publication/2013-05_21st-century-digital-design-tools)

[William Dally](/person/william-dally), Chris Malachosky, [Steve Keckler](/person/stephen-keckler)



[Design Automation Conference (DAC)](https://ieeexplore.ieee.org/document/6560687)









[A 0.54pJ/b 20Gb/s Ground-Referenced Single-Ended Short-Haul Serial Link in 28nm CMOS for Advanced Packaging Applications](/publication/2013-02_054pjb-20gbs-ground-referenced-single-ended-short-haul-serial-link-28nm-cmos)

John Poulton, [William Dally](/person/william-dally), [Xi Chen](/person/xi-chen), John Eyles, [Trey Greer](/person/trey-greer), [Stephen Tell](/person/stephen-tell), [Tom Gray](/person/tom-gray)



[ISSCC](http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6487789)









### 2010 

[The Even/Odd Synchronizer: A Fast, All-Digital Periodic Synchronizer](/index.php/publication/2010-05_evenodd-synchronizer-fast-all-digital-periodic-synchronizer)

[William Dally](/index.php/person/william-dally), [Stephen Tell](/index.php/person/stephen-tell)



[16th International Symposium on Asynchronous Circuits and Systems](https://ieeexplore.ieee.org/document/5476986)









### 2007 

[A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS](/index.php/publication/2007-12_14-mw-625-gbs-transceiver-90-nm-cmos)

John Poulton, Robert Palmer, Andy Fuller, [Trey Greer](/index.php/person/trey-greer), John Eyles, [William Dally](/index.php/person/william-dally), Mark Horowitz



[IEEE Journal of Solid-State Circuits](http://www.ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=4)









 

 



 ### Researchers

 

[Ahmed Nabih](/person/ahmed-nabih)



[Ben Keller](/person/ben-keller)



[Ben Lee](/index.php/person/ben-lee)



[Brent Keeth](/person/brent-keeth)



[Brian Zimmer](/person/brian-zimmer)



[Charbel Sakr](/index.php/person/charbel-sakr)



[Chenhui Deng](/person/chenhui-deng)



[Chia-Tung (Mark) Ho](/index.php/person/chia-tung-mark-ho)



[Cunxi Yu](/person/cunxi-yu)



[Dennis Abts](/person/dennis-abts)



[Donghyuk Lee](/person/donghyuk-lee)



[Georgios Kalogerakis](/person/georgios-kalogerakis)



[Guan-Ting (Danny) Liu](/person/guan-ting-danny-liu)



[Haoyu Yang](/person/haoyu-yang)



[Hasan Nazim Genc](/person/hasan-nazim-genc)



[John Wilson](/index.php/person/john-wilson)



[Li Xu](/person/li-xu)



[Liron Gantz](/person/liron-gantz)



[Mahmut Ersin Sinangil](/person/mahmut-sinangil)



[Marina Neseem](/person/marina-neseem)



[Matt Fojtik](/person/matt-fojtik)



[Matthijs Van keirsbilck](/person/matthijs-van-keirsbilck)



[Mingjie Liu](/person/mingjie-liu)



[Muya Chang](/index.php/person/muya-chang)



[Nicolai Oswald](/person/nicolai-oswald)



[Nikola Nedovic](/person/nikola-nedovic)



[Qijing Jenny Huang](/person/qijing-jenny-huang)



[Rangharajan Venkatesan](/person/rangharajan-venkatesan)



[Reena Elangovan](/index.php/person/reena-elangovan)



[Rongjian Liang](/person/rongjian-liang)



[Rose Abramson](/index.php/person/rose-abramson)



[Sanquan Song](/index.php/person/sanquan-song)



[Shai Cohen](/index.php/person/shai-cohen)



[Stephen Tell](/person/stephen-tell)



[Tom Gray](/person/tom-gray)



[Vikram Suresh](/person/vikram-suresh)



[Wen-Hao Liu](/index.php/person/wen-hao-liu)



[William Dally](/person/william-dally)



[Xi Chen](/index.php/person/xi-chen)



[Yan He](/person/yan-he)



[Yanqing Zhang](/person/yanqing-zhang)



[Yoshi Nishi](/index.php/person/yoshi-nishi)



[Youssef Elasser](/index.php/person/youssef-elasser)



[Yunsheng Bai](/person/yunsheng-bai)