Latest

• ReLS: Retrieval Is Efficient Knowledge Transfer For Logic Synthesis
• VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool
• Large Language Model (LLM) for Standard Cell Layout Design Optimization
• Novel Transformer Model Based Clustering Method for Standard Cell Design Automation
• NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model