Latest

• Differentiable Edge-based OPC
• ReLS: Retrieval Is Efficient Knowledge Transfer For Logic Synthesis
• Learning to Compare Hardware Designs for High-Level Synthesis
• Optimizing Predictive AI in Physical Design Flows with Mini Pixel Batch Gradient Descent
• VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool
• ILILT: Implicit Learning of Inverse Lithography Technologies
• Large Language Model (LLM) for Standard Cell Layout Design Optimization
• Challenges for Automating PCB Layout (Invited)
• RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models
• OpenROAD and CircuitOps: Infrastructure for ML EDA Research and Education
• Challenges for Automating PCB Layout (Invited)
• Novel Transformer Model Based Clustering Method for Standard Cell Design Automation
• GPU/ML-Enhanced Large Scale Global Routing Contest
• MedPart: A Multi-Level Evolutionary Differentiable Hypergraph Partitioner
• CircuitOps: An ML Infrastructure Enabling Generative AI for VLSI Circuit Optimization
• Late Breaking Results: Test Selection For RTL Coverage By Unsupervised Learning From Fast Functional Simulation
• GATSPI: GPU accelerated gate-level simulation for power improvement
• NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model
• Enabling scalable AI computational lithography with physics-inspired models
• BufFormer: A Generative ML Framework for Scalable Buffering
• Generic lithography modeling with dual-band optics-inspired neural networks
• Placement Optimization via PPA-Directed Graph Clustering
• GRANNITE: Graph Neural Network Inference for Transferable Power Estimation