Latest

• ReLS: Retrieval Is Efficient Knowledge Transfer For Logic Synthesis
• Learning to Compare Hardware Designs for High-Level Synthesis
• OpenROAD and CircuitOps: Infrastructure for ML EDA Research and Education
• DiMO-Sparse: Differentiable Modeling and Optimization of Sparse CNN Dataflow and Hardware Architecture
• GPU/ML-Enhanced Large Scale Global Routing Contest
• MedPart: A Multi-Level Evolutionary Differentiable Hypergraph Partitioner
• CircuitOps: An ML Infrastructure Enabling Generative AI for VLSI Circuit Optimization
• Late Breaking Results: Test Selection For RTL Coverage By Unsupervised Learning From Fast Functional Simulation
• BufFormer: A Generative ML Framework for Scalable Buffering