Latest

• INSTA: An Ultra-Fast, Differentiable, Statistical Static Timing Analysis Engine for Industrial Physical Design Applications
• DCO-3D: Differentiable Congestion Optimization in 3D ICs
• Reinforcement Learning-Driven Window Selection for Enhanced Window-Based Rip-up and Reroute in Chip Detailed Routing
• Hybrid Structured Clock Network Construction with GPUs for Large Designs
• LEGO-Size: LLM-Enhanced GPU-Optimized Signoff-Accurate Differentiable VLSI Gate Sizing in Advanced Nodes
• GOALPlace: Begin with the End in Mind
• Hybrid Exact and Heuristic Efficient Transistor Network Optimization for Multi-Output Logic
• Invited: ISPD 2025 Performance-Driven Large Scale Global Routing Contest
• DiMO-CNN: Deep Learning Toolkit-Accelerated Analytical Modeling and Optimization of CNN Hardware and Dataflow
• Invited Paper: 2024 ICCAD CAD Contest Problem C: Scalable Logic Gate Sizing using ML Techniques and GPU Acceleration
• ReLS: Retrieval Is Efficient Knowledge Transfer For Logic Synthesis
• Learning to Compare Hardware Designs for High-Level Synthesis
• OpenROAD and CircuitOps: Infrastructure for ML EDA Research and Education
• DiMO-Sparse: Differentiable Modeling and Optimization of Sparse CNN Dataflow and Hardware Architecture
• GPU/ML-Enhanced Large Scale Global Routing Contest
• MedPart: A Multi-Level Evolutionary Differentiable Hypergraph Partitioner
• CircuitOps: An ML Infrastructure Enabling Generative AI for VLSI Circuit Optimization
• Late Breaking Results: Test Selection For RTL Coverage By Unsupervised Learning From Fast Functional Simulation
• BufFormer: A Generative ML Framework for Scalable Buffering