Latest

• C3PO: Commercial-Quality Global Placement via Coherent, Concurrent Timing, Routability, and Wirelength Optimization
• 2025 ICCAD CAD Contest Problem C: Incremental Placement Optimization Beyond Detailed Placement: Simultaneous Gate Sizing, Buffering, and Cell Relocation
• Netlistify: Transforming Circuit Schematics into Netlists with Deep Learning
• Reinforcement Learning-Driven Window Selection for Enhanced Window-Based Rip-up and Reroute in Chip Detailed Routing
• Hybrid Structured Clock Network Construction with GPUs for Large Designs
• Overflow-Aware Via Placement for Dense Die-to-Die Connections in Advanced Package Routing
• River Segments Detection Strategy for Advanced Packages Routing
• Invited: ISPD 2025 Performance-Driven Large Scale Global Routing Contest
• ReLS: Retrieval Is Efficient Knowledge Transfer For Logic Synthesis
• Challenges for Automating PCB Layout (Invited)
• Challenges for Automating PCB Layout (Invited)
• GPU/ML-Enhanced Large Scale Global Routing Contest