Latest

• C3PO: Commercial-Quality Global Placement via Coherent, Concurrent Timing, Routability, and Wirelength Optimization
• Differentiable Tier Assignment for Timing and Congestion-Aware Routing in 3D ICs
• 2025 ICCAD CAD Contest Problem C: Incremental Placement Optimization Beyond Detailed Placement: Simultaneous Gate Sizing, Buffering, and Cell Relocation
• BUFFALO: PPA-Configurable, LLM-based Buffer Tree Generation via Group Relative Policy Optimization
• LLM-Enhanced GPU-Optimized Physical Design at Scale (invited)
• INSTA: An Ultra-Fast, Differentiable, Statistical Static Timing Analysis Engine for Industrial Physical Design Applications
• DCO-3D: Differentiable Congestion Optimization in 3D ICs
• LEGO-Size: LLM-Enhanced GPU-Optimized Signoff-Accurate Differentiable VLSI Gate Sizing in Advanced Nodes
• Placement Optimization via PPA-Directed Graph Clustering