Angshuman Parashar ![](/sites/default/files/person/mugshot.jpg) Dr. Angshuman Parashar joined NVIDIA in 2015 and is a member of the Architecture Research Group. His research focuses on building and evaluating architectures for spatial and data-parallel algorithms. Prior to NVIDIA, he was a member of the VSSAD group at Intel, where he worked with a small team of experts in architecture, languages, workloads and implementation to design and evaluate a new spatial architecture. Parashar received his Ph.D. in Computer Science and Engineering from the Pennsylvania State University in 2007, and his B.Tech. in Computer Science and Engineering from the Indian Institute of Technology, Delhi in 2002. [List of publications](http://www.parashar.org/?page_id=5) Research Area(s) [Artificial Intelligence and Machine Learning ](/research-area/machine-learning-artificial-intelligence) Main Field of Interest [Computer Architecture](/research-area/computer-architecture) ### Publications ### 2022 [Demystifying Map Space Exploration for NPUs](/index.php/publication/2022-11_demystifying-map-space-exploration-npus) Sheng-Chun Kao, [Angshuman Parashar](/index.php/person/angshuman-parashar), [Po-An Tsai](/index.php/person/po-an-tsai), Tushar Krishna [International Symposium on Workload Characterization (IISWC)](https://ieeexplore.ieee.org/document/9975389) [Sparseloop: An Analytical Approach to Sparse Tensor Accelerator Modeling](/index.php/publication/2022-10_sparseloop-analytical-approach-sparse-tensor-accelerator-modeling) Yannan Nellie Wu, [Po-An Tsai](/index.php/person/po-an-tsai), [Angshuman Parashar](/index.php/person/angshuman-parashar), Vivienne Sze, [Joel Emer](/index.php/person/joel-emer) [International Symposium on Microarchitecture (MICRO)](https://ieeexplore.ieee.org/document/9923807) Distinguished Artifact award [Ruby: Improving Hardware Efficiency for Tensor Algebra Accelerators Through Imperfect Factorization](/index.php/publication/2022-06_ruby-improving-hardware-efficiency-tensor-algebra-accelerators-through) Mark Horeni, Pooria Taheri, [Po-An Tsai](/index.php/person/po-an-tsai), [Angshuman Parashar](/index.php/person/angshuman-parashar), [Joel Emer](/index.php/person/joel-emer), Siddharth Joshi [International Symposium on Performance Analysis of Systems and Software (ISPASS)](https://ieeexplore.ieee.org/document/9804679) [A Formalism of DNN Accelerator Flexibility](/index.php/publication/2022-06_formalism-dnn-accelerator-flexibility) Sheng-Chun Kao, Hyoukjun Kwon, [Michael Pellauer](/index.php/person/michael-pellauer), [Angshuman Parashar](/index.php/person/angshuman-parashar), Tushar Krishna [SIGMETRICS](https://dl.acm.org/doi/abs/10.1145/3530907) [DiGamma: Domain-aware Genetic Algorithm for HW-Mapping Co-optimization for DNN Accelerators](/publication/2022-03_digamma-domain-aware-genetic-algorithm-hw-mapping-co-optimization-dnn) Sheng-Chun Kao, [Michael Pellauer](/person/michael-pellauer), [Angshuman Parashar](/person/angshuman-parashar), Tushar Krishna [Design, Automation & Test in Europe (DATE)](https://dl.acm.org/doi/abs/10.5555/3539845.3539906) [Marvel: A Data-Centric Approach for Mapping Deep Learning Operators on Spatial Accelerators](/index.php/publication/2022-03_marvel-data-centric-approach-mapping-deep-learning-operators-spatial) Prasanth Chatarasi, Hyoukjun Kwon, [Angshuman Parashar](/index.php/person/angshuman-parashar), [Michael Pellauer](/index.php/person/michael-pellauer), Tushar Krishna, Vivek Sarkar [Transactions on Architecture and Code Optimization (TACO)](https://dl.acm.org/doi/full/10.1145/3485137) ### 2021 [Union: A Unified HW-SW Co-Design Ecosystem in MLIR for Evaluating Tensor Operations on Spatial Accelerators](/index.php/publication/2021-09_union-unified-hw-sw-co-design-ecosystem-mlir-evaluating-tensor-operations) Geonhwa Jeong, Gokcen Kestor, Prasanth Chatarasi, [Angshuman Parashar](/index.php/person/angshuman-parashar), [Po-An Tsai](/index.php/person/po-an-tsai), Sivasankaran Rajamanickam, Roberto Gioiosa, Tushar Krishna [Parallel Architectures and Compilation Techniques (PACT)](https://ieeexplore.ieee.org/document/9563040) [Sparseloop: An Analytical, Energy-Focused Design Space Exploration Methodology for Sparse Tensor Accelerators](/index.php/publication/2021-04_sparseloop-analytical-energy-focused-design-space-exploration-methodology) Yannan Nellie Wu, [Po-An Tsai](/index.php/person/po-an-tsai), [Angshuman Parashar](/index.php/person/angshuman-parashar), Vivienne Sze, [Joel Emer](/index.php/person/joel-emer) [International Symposium on Performance Analysis of Systems and Software (ISPASS)](https://ieeexplore.ieee.org/document/9408213) [Mind Mappings: Enabling Efficient Algorithm-Accelerator Mapping Space Search](/index.php/publication/2021-04_mind-mappings-enabling-efficient-algorithm-accelerator-mapping-space-search) Kartik Hegde, [Po-An Tsai](/index.php/person/po-an-tsai), Sitao Huang, Vikas Chandra, [Angshuman Parashar](/index.php/person/angshuman-parashar), Christopher W. Fletcher [International Conference on Architectural Support for Programming Languages and…](https://dl.acm.org/doi/10.1145/3445814.3446762) [Hardware Abstractions for Targeting EDDO Architectures with the Polyhedral Model](/index.php/publication/2021-01_hardware-abstractions-targeting-eddo-architectures-polyhedral-model) [Angshuman Parashar](/index.php/person/angshuman-parashar), Prasanth Chatarasi, [Po-An Tsai](/index.php/person/po-an-tsai) [International Workshop on Polyhedral Compilation Techniques (IMPACT)](https://acohen.gitlabpages.inria.fr/impact/impact2021/) [Flexion: A Quantitative Metric for Flexibility in DNN Accelerators](/index.php/publication/2021-01_flexion-quantitative-metric-flexibility-dnn-accelerators) Hyoukjun Kwon, [Michael Pellauer](/index.php/person/michael-pellauer), [Angshuman Parashar](/index.php/person/angshuman-parashar), Tushar Krishna [IEEE Computer Architecture Letters (CAL)](https://ieeexplore.ieee.org/document/9293373) ### 2020 [MAESTRO: A Data-Centric Approach to Understand Reuse, Performance, and Hardware Cost of DNN Mappings](/index.php/publication/2020-04_maestro-data-centric-approach-understand-reuse-performance-and-hardware-cost) Hyoukjun Kwon, Prasanth Chatarasi, Vivek Sarkar, Tushar Krishna, [Michael Pellauer](/index.php/person/michael-pellauer), [Angshuman Parashar](/index.php/person/angshuman-parashar) [IEEE Micro (Issue: Top Picks of the 2019 Computer Architecture Conferences)](https://ieeexplore.ieee.org/document/9076333) ### 2019 [Understanding Reuse, Performance, and Hardware Cost of DNN Dataflows: A Data-Centric Approach.](/index.php/publication/2019-10_understanding-reuse-performance-and-hardware-cost-dnn-dataflows-data-centric) Hyoukjun Kwon, Prasanth Chatarasi, [Michael Pellauer](/index.php/person/michael-pellauer), [Angshuman Parashar](/index.php/person/angshuman-parashar), Vivek Sarkar, Tushar Krishna [International Symposium on Microarchitecture (MICRO)](https://dl.acm.org/doi/10.1145/3352460.3358252) IEEE Micro Top Picks in Computer Architecture [Timeloop: A Systematic Approach to DNN Accelerator Evaluation](/publication/2019-03_timeloop-systematic-approach-dnn-accelerator-evaluation) [Angshuman Parashar](/person/angshuman-parashar), Priyanka Raina, Yakun Sophia Shao, Yu-Hsin Chen, Victor A. Ying, Anurag Mukkara, [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Brucek Khailany](/person/brucek-khailany), [Steve Keckler](/person/stephen-keckler), [Joel Emer](/person/joel-emer) [International Symposium on Performance Analysis of Systems and Software (ISPASS)](https://ieeexplore.ieee.org/document/8695666) ### 2018 [Stitch-X: An Accelerator Architecture for Exploiting Unstructured Sparsity in Deep Neural Networks](/index.php/publication/2018-02_stitch-x-accelerator-architecture-exploiting-unstructured-sparsity-deep-neural) Ching-En Lee, Yakun Sophia Shao, Jie-Fang Zhang, [Angshuman Parashar](/index.php/person/angshuman-parashar), [Joel Emer](/index.php/person/joel-emer), [Steve Keckler](/index.php/person/stephen-keckler), Zhengya Zhang [SysML Conference](https://mlsys.org/Conferences/2018/index.html#posters) ### 2017 [SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks](/publication/2017-06_scnn-accelerator-compressed-sparse-convolutional-neural-networks) [Angshuman Parashar](/person/angshuman-parashar), Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Brucek Khailany](/person/brucek-khailany), [Joel Emer](/person/joel-emer), [Steve Keckler](/person/stephen-keckler), [William Dally](/person/william-dally) [International Symposium on Computer Architecture (ISCA)](https://dl.acm.org/doi/10.1145/3079856.3080254) [SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks](/index.php/publication/2017-05_scnn-accelerator-compressed-sparse-convolutional-neural-networks) [Angshuman Parashar](/index.php/person/angshuman-parashar), Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, [Rangharajan Venkatesan](/index.php/person/rangharajan-venkatesan), [Brucek Khailany](/index.php/person/brucek-khailany), [Joel Emer](/index.php/person/joel-emer), [Steve Keckler](/index.php/person/stephen-keckler), [William Dally](/index.php/person/william-dally) [arXiv](https://arxiv.org/abs/1708.04485) ### 2015 [Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures](/publication/2015-09_efficient-control-and-communication-paradigms-coarse-grained-spatial) [Michael Pellauer](/person/michael-pellauer), [Angshuman Parashar](/person/angshuman-parashar), Michael Adler, Bushra Ahsan, Randy Almon, [Neal Crago](/person/neal-crago), Kermin Fleming, Mohit Gambhir, [Aamer Jaleel](/person/aamer-jaleel), Tushar Krishna, [Daniel Lustig](/person/daniel-lustig), Stephen Maresh, Vladimir Pavlov, Rachid Rayess, Antonia Zhai, [Joel Emer](/person/joel-emer) [ACM Transactions on Computing Systems (TOCS)](https://dl.acm.org/doi/10.1145/2754930)