Ben Keller  

 



  ![](/sites/default/files/person/Me3.1.png)

  

 Ben joined the Accelerators & VLSI research group at NVIDIA in 2017 after an internship with the group three years earlier. His research interests include energy-efficient deep learning inference accelerator design, clocking and synchronization, and improved methodologies for ASIC design effort reduction.

Ben received his M.S. and Ph.D. degrees in Electrical Engineering and Computer Sciences from the University of California, Berkeley, in 2015 and 2017, respectively. He completed his B.S. in Engineering at Harvey Mudd College in 2010.



   Research Area(s)

[Artificial Intelligence and Machine Learning ](/research-area/machine-learning-artificial-intelligence)

[Circuits and VLSI Design](/research-area/circuits)

[Computer Architecture](/research-area/computer-architecture)

 

 

  

 Main Field of Interest

[Circuits and VLSI Design](/research-area/circuits)

 

  

 Google Scholar

<https://scholar.google.com/citations?user=D-hDMb4AAAAJ>

 

  

 

 

 



 ### Publications

 

### 2026 

[GalaxyDiT: Efficient Video Generation with Guidance Alignment and Adaptive Proxy in Diffusion Transformers](/publication/2026-07_galaxydit-efficient-video-generation-guidance-alignment-and-adaptive-proxy)

Zoey Song, [Steve Dai](/person/steve-dai), [Ben Keller](/person/ben-keller), [Brucek Khailany](/person/brucek-khailany)



[DAC 2026](https://dac.com/2026)









[Alpha-Vision: A Real-Time Always-on Vision Processor with 787µs Face Detection Latency in &lt;5mW](/publication/2026-02_alpha-vision-real-time-always-vision-processor-787ms-face-detection-latency)

[Ben Keller](/person/ben-keller), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Steve Dai](/person/steve-dai), [Jason Clemons](/person/jason-clemons), [Matt Fojtik](/person/matt-fojtik), [Muya Chang](/person/muya-chang), Thierry Tambe, [Nathaniel Pinckney](/person/nathaniel-pinckney), [Stephen Tell](/person/stephen-tell), [Qijing Jenny Huang](/person/qijing-jenny-huang), [Shalini De Mello](/person/shalini-de-mello), [Brucek Khailany](/person/brucek-khailany)



[ISSCC 2026](https://www.isscc.org/)









### 2025 

[GauRast: Enhancing GPU Triangle Rasterizers to Accelerate 3D Gaussian Splatting](/publication/2025-06_gaurast-enhancing-gpu-triangle-rasterizers-accelerate-3d-gaussian-splatting)

Sixu Li, [Ben Keller](/person/ben-keller), Yingyan Celine Lin, [Brucek Khailany](/person/brucek-khailany)



[Design Automation Conference (DAC)](https://arxiv.org/abs/2503.16681)









### 2023 

[AutoDMP: Automated DREAMPlace-based Macro Placement](/publication/2023-03_autodmp-automated-dreamplace-based-macro-placement)

Anthony Agnesina, Puranjay Rajvanshi, Tian Yang, Geraldo Pradipta, Austin Jiao, [Ben Keller](/person/ben-keller), [Brucek Khailany](/person/brucek-khailany), Mark Haoxing Ren



[International Symposium on Physical Design 2023](https://ispd.cc/ispd2023/index.php)









[A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm](/publication/2023-01_956-topsw-deep-learning-inference-accelerator-vector-scaled-4-bit-quantization)

[Ben Keller](/person/ben-keller), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Steve Dai](/person/steve-dai), [Stephen Tell](/person/stephen-tell), [Brian Zimmer](/person/brian-zimmer), [Charbel Sakr](/person/charbel-sakr), [William Dally](/person/william-dally), [Tom Gray](/person/tom-gray), [Brucek Khailany](/person/brucek-khailany)



[Journal of Solid-State Circuits](https://ieeexplore.ieee.org/document/10019275)









### 2022 

[HEAT: Hardware-Efficient Automatic Tensor Decomposition for Transformer Compression](/publication/2022-12_heat-hardware-efficient-automatic-tensor-decomposition-transformer-compression)

Jiaqi Gu, [Ben Keller](/person/ben-keller), [Jean Kossaifi](/person/jean-kossaifi), Anima Anandkumar, [Brucek Khailany](/person/brucek-khailany), David Z. Pan



[Workshop on ML for Systems at NeurIPS](http://mlforsystems.org)



Spotlight Paper





[XT-PRAGGMA: Crosstalk Pessimism Reduction Accessible by GPU Gate-level Simulations and Machine Learning](/publication/2022-09_xt-praggma-crosstalk-pessimism-reduction-accessible-gpu-gate-level-simulations)

Vidya Chhabria, [Ben Keller](/person/ben-keller), [Yanqing Zhang](/person/yanqing-zhang), Sandeep Vollala, Sreedhar Patty, Mark Haoxing Ren, [Brucek Khailany](/person/brucek-khailany)



[MLCAD '22: Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD](https://mlcad-workshop.org/)









[A 17–95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm](/publication/2022-06_17-956-topsw-deep-learning-inference-accelerator-vector-scaled-4-bit)

[Ben Keller](/person/ben-keller), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Steve Dai](/person/steve-dai), [Stephen Tell](/person/stephen-tell), [Brian Zimmer](/person/brian-zimmer), [William Dally](/person/william-dally), [Tom Gray](/person/tom-gray), [Brucek Khailany](/person/brucek-khailany)



[2022 Symposium on VLSI Technology &amp; Circuits Digest of Technical Papers](https://www.vlsisymposium.org)









### 2021 

[IPA: Floorplan-Aware SystemC Interconnect Performance Modeling and Generation for HLS-based SoCs](/publication/2021-11_ipa-floorplan-aware-systemc-interconnect-performance-modeling-and-generation)

[Nathaniel Pinckney](/person/nathaniel-pinckney), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Ben Keller](/person/ben-keller), [Brucek Khailany](/person/brucek-khailany)



[IEEE/ACM International Conference on Computer-Aided Design (ICCAD ’21)](https://iccad.com/)









[Simba: scaling deep-learning inference with chiplet-based architecture](/publication/2021-05_simba-scaling-deep-learning-inference-chiplet-based-architecture)

Yakun Sophia Shao, [Jason Clemons](/person/jason-clemons), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Brian Zimmer](/person/brian-zimmer), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Brucek Khailany](/person/brucek-khailany), [Steve Keckler](/person/stephen-keckler)



[Communications of the ACM](https://dl.acm.org/doi/10.1145/3460227)



ACM Research Highlight





[Verifying High-Level Latency-Insensitive Designs with Formal Model Checking](/publication/2021-02_verifying-high-level-latency-insensitive-designs-formal-model-checking)

[Steve Dai](/person/steve-dai), Alicia Klinefelter, Mark Haoxing Ren, [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Ben Keller](/person/ben-keller), [Nathaniel Pinckney](/person/nathaniel-pinckney), [Brucek Khailany](/person/brucek-khailany)



[arXiv](https://arxiv.org/abs/2102.06326)









[MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification](/publication/2021-02_mavirec-ml-aided-vectored-ir-drop-estimation-and-classification)

Vidya A. Chhabria, [Yanqing Zhang](/person/yanqing-zhang), Mark Haoxing Ren, [Ben Keller](/person/ben-keller), [Brucek Khailany](/person/brucek-khailany), Sachin S. Sapatnekar



[2021 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)](https://www.date-conference.com/)









### 2020 

[Accelerating Chip Design with Machine Learning](/publication/2020-09_accelerating-chip-design-machine-learning)

[Brucek Khailany](/person/brucek-khailany), Mark Haoxing Ren, [Steve Dai](/person/steve-dai), Saad Godil, [Ben Keller](/person/ben-keller), Robert Kirby, Alicia Klinefelter, [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Yanqing Zhang](/person/yanqing-zhang), Bryan Catanzaro, [William Dally](/person/william-dally)



[IEEE Micro](https://ieeexplore.ieee.org/document/9205654)









[A 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm](/publication/2020-01_032-128-tops-scalable-multi-chip-module-based-deep-neural-network-inference)

[Brian Zimmer](/person/brian-zimmer), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), Yakun Sophia Shao, [Jason Clemons](/person/jason-clemons), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Steve Keckler](/person/stephen-keckler), [Brucek Khailany](/person/brucek-khailany)



[IEEE Journal of Solid-State Circuits (JSSC)](https://ieeexplore.ieee.org/document/8959403)



JSSC 2020 Best Paper award





### 2019 

[MAGNet: A Modular Accelerator Generator for Neural Networks](/publication/2019-11_magnet-modular-accelerator-generator-neural-networks)

[Rangharajan Venkatesan](/person/rangharajan-venkatesan), Sophia Shao, Miaorong Wang, [Jason Clemons](/person/jason-clemons), [Steve Dai](/person/steve-dai), [Matt Fojtik](/person/matt-fojtik), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Yanqing Zhang](/person/yanqing-zhang), [Brian Zimmer](/person/brian-zimmer), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Steve Keckler](/person/stephen-keckler), [Brucek Khailany](/person/brucek-khailany)



[International Conference On Computer Aided Design (ICCAD)](https://ieeexplore.ieee.org/document/8942127)









[Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture](/publication/2019-10_simba-scaling-deep-learning-inference-multi-chip-module-based-architecture)

Sophia Shao, [Jason Clemons](/person/jason-clemons), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Brian Zimmer](/person/brian-zimmer), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Brucek Khailany](/person/brucek-khailany), [Steve Keckler](/person/stephen-keckler)



[International Symposium on Microarchitecture (MICRO)](https://dl.acm.org/doi/10.1145/3352460.3358302)



Best Paper award, IEEE Micro Top Picks in Computer Architecture (Honorable Mention)





[A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator Designed with a High-Productivity VLSI Methodology](/publication/2019-08_011-pjop-032-128-tops-scalable-multi-chip-module-based-deep-neural-network)

[Rangharajan Venkatesan](/person/rangharajan-venkatesan), Sophia Shao, [Brian Zimmer](/person/brian-zimmer), [Jason Clemons](/person/jason-clemons), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Steve Keckler](/person/stephen-keckler), [Brucek Khailany](/person/brucek-khailany)



[Hot Chips: A Symposium on High Performance Chips](http://www.hotchips.org/)









[A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm](/publication/2019-06_011-pjop-032-128-tops-scalable-multi-chip-module-based-deep-neural-network)

[Brian Zimmer](/person/brian-zimmer), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), Sophia Shao, [Jason Clemons](/person/jason-clemons), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Steve Keckler](/person/stephen-keckler), [Brucek Khailany](/person/brucek-khailany)



[Symposium on VLSI Circuits](https://ieeexplore.ieee.org/document/8778056)









[PRIMAL: Power Inference using Machine Learning](/publication/2019-06_primal-power-inference-using-machine-learning)

Yuan Zhou, Mark Haoxing Ren, [Yanqing Zhang](/person/yanqing-zhang), [Ben Keller](/person/ben-keller), [Brucek Khailany](/person/brucek-khailany), Zhiru Zhang



[Design Automation Conference (DAC)](https://dac.com/)









[A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET](/publication/2019-05_fine-grained-gals-soc-pausible-adaptive-clocking-16-nm-finfet)

[Matt Fojtik](/person/matt-fojtik), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), [Stephen Tell](/person/stephen-tell), [Brian Zimmer](/person/brian-zimmer), Tezaswi Raja, Kevin Zhou, [William Dally](/person/william-dally), [Brucek Khailany](/person/brucek-khailany)



[ASYNC 2019](http://www.async2019.jp/)



ASYNC 2019 Best Paper Award