Brian Zimmer ![](/sites/default/files/person/bzimmer_0.jpg) Brian Zimmer joined the Circuits Research Group in NVIDIA Research in 2015. His research interests are in energy-efficient digital design, with an emphasis on low-voltage SRAM design and variation tolerance. He received the B.S. degree in electrical engineering from the University of California at Davis in 2010. He received the M.S. and Ph.D. degrees in electrical engineering and computer sciences from the University of California at Berkeley in 2012 and 2015, respectively. During the summer in 2012, he was an intern at Nvidia in the Circuits Research Group. Research Area(s) [Circuits and VLSI Design](/research-area/circuits) [Resilience and Safety](/research-area/resilience) Main Field of Interest [Circuits and VLSI Design](/research-area/circuits) Google Scholar [https://scholar.google.com/citations?user=WH4-bRkAAAAJ&hl=en&oi=ao](https://scholar.google.com/citations?user=WH4-bRkAAAAJ&hl=en&oi=ao) ### Publications ### 2024 [A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS](/publication/2024-04_0190-pjbit-252-gbswire-inverter-based-ac-coupled-transceiver-short-reach-die) [Yoshinori Nishi](/person/yoshi-nishi), John W. Poulton, [Xi Chen](/person/xi-chen), [Sanquan Song](/person/sanquan-song), [Brian Zimmer](/person/brian-zimmer), [Walker Turner](/person/walker-turner), [Stephen Tell](/person/stephen-tell), [Nikola Nedovic](/person/nikola-nedovic), [John Wilson](/person/john-wilson), [William Dally](/person/william-dally), [Tom Gray](/person/tom-gray) [IEEE Journal of Solid-State Circuits (JSSC) (Volume: 59, Issue: 4, April 2024)](https://ieeexplore.ieee.org/document/10185334) ### 2023 [A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS](/publication/2023-06_0190-pjbit-252-gbswire-inverter-based-ac-coupled-transceiver-short-reach-die) [Yoshinori Nishi](/person/yoshi-nishi), John W. Poulton, [Xi Chen](/person/xi-chen), [Sanquan Song](/person/sanquan-song), [Brian Zimmer](/person/brian-zimmer), [Walker Turner](/person/walker-turner), [Stephen Tell](/person/stephen-tell), [Nikola Nedovic](/person/nikola-nedovic), [John Wilson](/person/john-wilson), [William Dally](/person/william-dally), [Tom Gray](/person/tom-gray) [2023 IEEE SYMPOSIUM ON VLSI TECHNOLOGY & CIRCUITS](https://ieeexplore.ieee.org/abstract/document/10185334) [A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS](/publication/2023-04_0297-pjbit-504-gbswire-inverter-based-short-reach-simultaneous-bi-directional) [Yoshinori Nishi](/person/yoshi-nishi), John W. Poulton, [Walker Turner](/person/walker-turner), [Xi Chen](/person/xi-chen), [Sanquan Song](/person/sanquan-song), [Brian Zimmer](/person/brian-zimmer), [Stephen Tell](/person/stephen-tell), [Nikola Nedovic](/person/nikola-nedovic), [John Wilson](/person/john-wilson), [William Dally](/person/william-dally), [Tom Gray](/person/tom-gray) [IEEE Journal of Solid-State Circuits ( Volume: 58, Issue: 4, April 2023)](https://ieeexplore.ieee.org/document/10011563) [A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm](/publication/2023-01_956-topsw-deep-learning-inference-accelerator-vector-scaled-4-bit-quantization) [Ben Keller](/person/ben-keller), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Steve Dai](/person/steve-dai), [Stephen Tell](/person/stephen-tell), [Brian Zimmer](/person/brian-zimmer), [Charbel Sakr](/person/charbel-sakr), [William Dally](/person/william-dally), [Tom Gray](/person/tom-gray), [Brucek Khailany](/person/brucek-khailany) [Journal of Solid-State Circuits](https://ieeexplore.ieee.org/document/10019275) ### 2022 [LNS-Madam: Low-Precision Training in Logarithmic Number System Using Multiplicative Weight Update](/publication/2022-12_lns-madam-low-precision-training-logarithmic-number-system-using-multiplicative) Jiawei Zhao, [Steve Dai](/person/steve-dai), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Brian Zimmer](/person/brian-zimmer), Mustafa Ali, [Ming-Yu Liu](/person/ming-yu-liu), [Brucek Khailany](/person/brucek-khailany), [William Dally](/person/william-dally), Anima Anandkumar [IEEE Transactions on Computers (Volume: 71, Issue: 12, 01 December 2022)](https://www.computer.org/csdl/journal/tc) [Optimal Clipping and Magnitude-aware Differentiation for Improved Quantization-aware Training](/publication/2022-07_optimal-clipping-and-magnitude-aware-differentiation-improved-quantization) [Charbel Sakr](/person/charbel-sakr), [Steve Dai](/person/steve-dai), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Brian Zimmer](/person/brian-zimmer), [Brucek Khailany](/person/brucek-khailany), [William Dally](/person/william-dally) [2022 International Conference on Machine Learning (ICML)](https://arxiv.org/abs/2206.06501) [A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS](/publication/2022-06_0297-pjbit-504-gbswire-inverter-based-short-reach-simultaneous-bidirectional) [Yoshinori Nishi](/person/yoshi-nishi), John W. Poulton, [Xi Chen](/person/xi-chen), [Sanquan Song](/person/sanquan-song), [Brian Zimmer](/person/brian-zimmer), [Walker Turner](/person/walker-turner), [Stephen Tell](/person/stephen-tell), [Nikola Nedovic](/person/nikola-nedovic), [John Wilson](/person/john-wilson), [William Dally](/person/william-dally), [Tom Gray](/person/tom-gray) [2022 IEEE SYMPOSIUM ON VLSI TECHNOLOGY & CIRCUITS](https://archive.vlsisymposium.org/22web/about/) [A 17–95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm](/index.php/publication/2022-06_17-956-topsw-deep-learning-inference-accelerator-vector-scaled-4-bit) [Ben Keller](/index.php/person/ben-keller), [Rangharajan Venkatesan](/index.php/person/rangharajan-venkatesan), [Steve Dai](/index.php/person/steve-dai), [Stephen Tell](/index.php/person/stephen-tell), [Brian Zimmer](/index.php/person/brian-zimmer), [William Dally](/index.php/person/william-dally), [Tom Gray](/index.php/person/tom-gray), [Brucek Khailany](/index.php/person/brucek-khailany) [2022 Symposium on VLSI Technology & Circuits Digest of Technical Papers](https://www.vlsisymposium.org) [AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies](/index.php/publication/2022-03_autocraft-layout-automation-custom-circuits-advanced-finfet-technologies) Hao Chen, [Walker Turner](/index.php/person/walker-turner), [Sanquan Song](/index.php/person/sanquan-song), Keren Zhu, George Kokai, [Brian Zimmer](/index.php/person/brian-zimmer), [Tom Gray](/index.php/person/tom-gray), [Brucek Khailany](/index.php/person/brucek-khailany), Mark Haoxing Ren [International Symposium on Physical Design 2022](https://ispd.cc/ispd2022/slides/ispd2022.html) ### 2021 [Simba: scaling deep-learning inference with chiplet-based architecture](/publication/2021-05_simba-scaling-deep-learning-inference-chiplet-based-architecture) Yakun Sophia Shao, [Jason Clemons](/person/jason-clemons), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Brian Zimmer](/person/brian-zimmer), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Brucek Khailany](/person/brucek-khailany), [Steve Keckler](/person/stephen-keckler) [Communications of the ACM](https://dl.acm.org/doi/10.1145/3460227) ACM Research Highlight [VS-QUANT: Per-Vector Scaled Quantization for Accurate Low-Precision Neural Network Inference](/publication/2021-04_vs-quant-vector-scaled-quantization-accurate-low-precision-neural-network) [Steve Dai](/person/steve-dai), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), Mark Haoxing Ren, [Brian Zimmer](/person/brian-zimmer), [William Dally](/person/william-dally), [Brucek Khailany](/person/brucek-khailany) [MLSys 2021](https://mlsys.org/) ### 2020 [Reference-Noise Compensation Scheme for Single- Ended Package-to-Package Links](/publication/2020-02_reference-noise-compensation-scheme-single-ended-package-package-links) [Xi Chen](/person/xi-chen), [Nikola Nedovic](/person/nikola-nedovic), [Stephen Tell](/person/stephen-tell), [Sudhir Kudva](/person/sudhir-kudva), [Brian Zimmer](/person/brian-zimmer), [Trey Greer](/person/trey-greer), John Poulton, [Sanquan Song](/person/sanquan-song), [Walker Turner](/person/walker-turner), [John Wilson](/person/john-wilson), [Tom Gray](/person/tom-gray) [2020 International Solid-State Circuits Conference](http://isscc.org/) [A 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm](/publication/2020-01_032-128-tops-scalable-multi-chip-module-based-deep-neural-network-inference) [Brian Zimmer](/person/brian-zimmer), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), Yakun Sophia Shao, [Jason Clemons](/person/jason-clemons), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Steve Keckler](/person/stephen-keckler), [Brucek Khailany](/person/brucek-khailany) [IEEE Journal of Solid-State Circuits (JSSC)](https://ieeexplore.ieee.org/document/8959403) JSSC 2020 Best Paper award ### 2019 [MAGNet: A Modular Accelerator Generator for Neural Networks](/publication/2019-11_magnet-modular-accelerator-generator-neural-networks) [Rangharajan Venkatesan](/person/rangharajan-venkatesan), Sophia Shao, Miaorong Wang, [Jason Clemons](/person/jason-clemons), [Steve Dai](/person/steve-dai), [Matt Fojtik](/person/matt-fojtik), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Yanqing Zhang](/person/yanqing-zhang), [Brian Zimmer](/person/brian-zimmer), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Steve Keckler](/person/stephen-keckler), [Brucek Khailany](/person/brucek-khailany) [International Conference On Computer Aided Design (ICCAD)](https://ieeexplore.ieee.org/document/8942127) [Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture](/publication/2019-10_simba-scaling-deep-learning-inference-multi-chip-module-based-architecture) Sophia Shao, [Jason Clemons](/person/jason-clemons), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Brian Zimmer](/person/brian-zimmer), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Brucek Khailany](/person/brucek-khailany), [Steve Keckler](/person/stephen-keckler) [International Symposium on Microarchitecture (MICRO)](https://dl.acm.org/doi/10.1145/3352460.3358302) Best Paper award, IEEE Micro Top Picks in Computer Architecture (Honorable Mention) [A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator Designed with a High-Productivity VLSI Methodology](/publication/2019-08_011-pjop-032-128-tops-scalable-multi-chip-module-based-deep-neural-network) [Rangharajan Venkatesan](/person/rangharajan-venkatesan), Sophia Shao, [Brian Zimmer](/person/brian-zimmer), [Jason Clemons](/person/jason-clemons), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Steve Keckler](/person/stephen-keckler), [Brucek Khailany](/person/brucek-khailany) [Hot Chips: A Symposium on High Performance Chips](http://www.hotchips.org/) [A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm](/publication/2019-06_011-pjop-032-128-tops-scalable-multi-chip-module-based-deep-neural-network) [Brian Zimmer](/person/brian-zimmer), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), Sophia Shao, [Jason Clemons](/person/jason-clemons), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Steve Keckler](/person/stephen-keckler), [Brucek Khailany](/person/brucek-khailany) [Symposium on VLSI Circuits](https://ieeexplore.ieee.org/document/8778056) [Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference](/publication/2019-06_analogmixed-signal-hardware-error-modeling-deep-learning-inference) Angad S. Rekhi, [Brian Zimmer](/person/brian-zimmer), [Nikola Nedovic](/person/nikola-nedovic), Nigxi Liu, [Rangharajan Venkatesan](/person/rangharajan-venkatesan), Miaorong Wang, [Brucek Khailany](/person/brucek-khailany), [William Dally](/person/william-dally), [Tom Gray](/person/tom-gray) [Design Automation Conference (DAC)](https://dac.com/) [A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET](/index.php/publication/2019-05_fine-grained-gals-soc-pausible-adaptive-clocking-16-nm-finfet) [Matt Fojtik](/index.php/person/matt-fojtik), [Ben Keller](/index.php/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/index.php/person/nathaniel-pinckney), [Stephen Tell](/index.php/person/stephen-tell), [Brian Zimmer](/index.php/person/brian-zimmer), Tezaswi Raja, Kevin Zhou, [William Dally](/index.php/person/william-dally), [Brucek Khailany](/index.php/person/brucek-khailany) [ASYNC 2019](http://www.async2019.jp/) ASYNC 2019 Best Paper Award [Voltage-Follower Coupling Quadrature Oscillator with Embedded Phase-Interpolator in 16nm FinFET](/index.php/publication/2019-04_voltage-follower-coupling-quadrature-oscillator-embedded-phase-interpolator) [Xi Chen](/index.php/person/xi-chen), [Sanquan Song](/index.php/person/sanquan-song), John Poulton, [Nikola Nedovic](/index.php/person/nikola-nedovic), [Brian Zimmer](/index.php/person/brian-zimmer), [Stephen Tell](/index.php/person/stephen-tell), [Tom Gray](/index.php/person/tom-gray) [IEEE Custom Integrated Circuits Conference 2019](http://ieee-cicc.org/) [A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator](/publication/2019-01_117-pjb-25-gbspin-ground-referenced-single-ended-serial-link-and-package) John Poulton, [John Wilson](/person/john-wilson), [Walker Turner](/person/walker-turner), [Brian Zimmer](/person/brian-zimmer), [Xi Chen](/person/xi-chen), [Sudhir Kudva](/person/sudhir-kudva), [Sanquan Song](/person/sanquan-song), [Stephen Tell](/person/stephen-tell), [Nikola Nedovic](/person/nikola-nedovic), Wenxu Zhao, Sunil Sudhakaran, [Tom Gray](/person/tom-gray), [William Dally](/person/william-dally) IEEE JOURNAL OF SOLID-STATE CIRCUITS ### 2018 [SwapCodes: Error Codes for Hardware-Software Cooperative GPU Pipeline Error Detection](/publication/2018-10_swapcodes-error-codes-hardware-software-cooperative-gpu-pipeline-error) [Michael B. Sullivan](/person/mike-sullivan), [Siva Hari](/person/siva-hari), [Brian Zimmer](/person/brian-zimmer), Timothy Tsai, [Stephen W. Keckler](/person/stephen-keckler) [The International Symposium on Microarchitecture (MICRO)](https://ieeexplore.ieee.org/document/8574584) [A Modular Digital VLSI Flow for High-Productivity SoC Design](/publication/2018-06_modular-digital-vlsi-flow-high-productivity-soc-design) [Brucek Khailany](/person/brucek-khailany), Evgeni Krimer, [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Jason Clemons](/person/jason-clemons), [Joel Emer](/person/joel-emer), [Matt Fojtik](/person/matt-fojtik), Alicia Klinefelter, [Michael Pellauer](/person/michael-pellauer), [Nathaniel Pinckney](/person/nathaniel-pinckney), Sophia Shao, Shreesha Srinath, Christopher Torng, Sam (Likun) Xi, [Yanqing Zhang](/person/yanqing-zhang), [Brian Zimmer](/person/brian-zimmer) [Design Automation Conference (DAC)](https://dl.acm.org/doi/10.1145/3195970.3199846) [Ground-Referenced Signaling for Intra-Chip and Short-Reach Chip-to-Chip Interconnects](/publication/2018-04_ground-referenced-signaling-intra-chip-and-short-reach-chip-chip-interconnects) [Walker Turner](/person/walker-turner), John Poulton, [John Wilson](/person/john-wilson), [Xi Chen](/person/xi-chen), [Stephen Tell](/person/stephen-tell), [Matt Fojtik](/person/matt-fojtik), [Trey Greer](/person/trey-greer), [Brian Zimmer](/person/brian-zimmer), [Sanquan Song](/person/sanquan-song), [Nikola Nedovic](/person/nikola-nedovic), [Sudhir Kudva](/person/sudhir-kudva), Sunil Sudhakaran, Rizwan Bashirullah, Wenxu Zhao, [William Dally](/person/william-dally), [Tom Gray](/person/tom-gray) Custom Integrated Circuits Conference [A 1.17pJ/b 25Gb/s/pin Ground-Referenced Single Ended Serial Link for Off- and On-Package Communication in 16nm CMOS Using a Process- and Temperature-Adaptive Voltage Regulator](/index.php/publication/2018-02_117pjb-25gbspin-ground-referenced-single-ended-serial-link-and-package) [John Wilson](/index.php/person/john-wilson), [Walker Turner](/index.php/person/walker-turner), John Poulton, [Brian Zimmer](/index.php/person/brian-zimmer), [Xi Chen](/index.php/person/xi-chen), [Sanquan Song](/index.php/person/sanquan-song), [Stephen Tell](/index.php/person/stephen-tell), [Nikola Nedovic](/index.php/person/nikola-nedovic), Wenxu Zhao, Sunil Sudhakaran, [Tom Gray](/index.php/person/tom-gray), [William Dally](/index.php/person/william-dally) ISSCC ### 2016 [An Analytical Model for Hardened Latch Selection and Exploration](/index.php/publication/2016-03_analytical-model-hardened-latch-selection-and-exploration) [Michael B. Sullivan](/index.php/person/mike-sullivan), [Brian Zimmer](/index.php/person/brian-zimmer), [Siva Hari](/index.php/person/siva-hari), Timothy Tsai, [Steve Keckler](/index.php/person/stephen-keckler) [Workshop on Silicon Errors in Logic--System Effects (SELSE)](http://www.selse.org/)