Matt Fojtik

  ![](/sites/default/files/person/matt-fojtik.jpg)

 ### Publications

### 2026

[Alpha-Vision: A Real-Time Always-on Vision Processor with 787µs Face Detection Latency in <5mW](/publication/2026-02_alpha-vision-real-time-always-vision-processor-787ms-face-detection-latency)

[Ben Keller](/person/ben-keller), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Steve Dai](/person/steve-dai), [Jason Clemons](/person/jason-clemons), [Matt Fojtik](/person/matt-fojtik), [Muya Chang](/person/muya-chang), Thierry Tambe, [Nathaniel Pinckney](/person/nathaniel-pinckney), [Stephen Tell](/person/stephen-tell), [Qijing Jenny Huang](/person/qijing-jenny-huang), [Shalini De Mello](/person/shalini-de-mello), [Brucek Khailany](/person/brucek-khailany)

[ISSCC 2026](https://www.isscc.org/)

### 2023

[NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model](/publication/2023-03_nvcell-2-routability-driven-standard-cell-layout-advanced-nodes-lattice-graph)

[Chia-Tung (Mark) Ho](/person/chia-tung-mark-ho), Alvin Ho, [Matt Fojtik](/person/matt-fojtik), Minsoo Kim, Shang Wei, Yaguang LI, [Brucek Khailany](/person/brucek-khailany), Mark Haoxing Ren

[International Symposium on Physical Design 2023](https://ispd.cc/ispd2023/index.php)

### 2022

[Machine Learning and Algorithms: Let Us Team Up for EDA](/index.php/publication/2022-01_machine-learning-and-algorithms-let-us-team-eda)

Mark Haoxing Ren, [Brucek Khailany](/index.php/person/brucek-khailany), [Matt Fojtik](/index.php/person/matt-fojtik), [Yanqing Zhang](/index.php/person/yanqing-zhang)

[IEEE Design & Test](https://ieee-ceda.org/publication/ieee-designtest)

### 2021

[NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning](/publication/2021-12_nvcell-standard-cell-layout-advanced-technology-nodes-reinforcement-learning)

Mark Haoxing Ren, [Matt Fojtik](/person/matt-fojtik), [Brucek Khailany](/person/brucek-khailany)

Design Automation Conference (DAC) 2021 (Invited special session paper)

[Simba: scaling deep-learning inference with chiplet-based architecture](/publication/2021-05_simba-scaling-deep-learning-inference-chiplet-based-architecture)

Yakun Sophia Shao, [Jason Clemons](/person/jason-clemons), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Brian Zimmer](/person/brian-zimmer), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Brucek Khailany](/person/brucek-khailany), [Steve Keckler](/person/stephen-keckler)

[Communications of the ACM](https://dl.acm.org/doi/10.1145/3460227)

ACM Research Highlight

[Standard Cell Routing with Reinforcement Learning and Genetic Algorithm in Advanced Technology Nodes](/index.php/publication/2021-01_standard-cell-routing-reinforcement-learning-and-genetic-algorithm-advanced)

Mark Haoxing Ren, [Matt Fojtik](/index.php/person/matt-fojtik)

[ 26th Asia and South Pacific Design Automation Conference (ASP-DAC) 2021](https://www.aspdac.com/aspdac2021/)

### 2020

[NVCell: Generate Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning](/index.php/publication/2020-12_nvcell-generate-standard-cell-layout-advanced-technology-nodes-reinforcement)

Mark Haoxing Ren, [Matt Fojtik](/index.php/person/matt-fojtik), [Brucek Khailany](/index.php/person/brucek-khailany)

[ Workshop on ML for Systems at NeurIPS](https://mlforsystems.org/assets/papers/neurips2020/nvcell_ren_2020.pdf)

[A 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm](/publication/2020-01_032-128-tops-scalable-multi-chip-module-based-deep-neural-network-inference)

[Brian Zimmer](/person/brian-zimmer), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), Yakun Sophia Shao, [Jason Clemons](/person/jason-clemons), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Steve Keckler](/person/stephen-keckler), [Brucek Khailany](/person/brucek-khailany)

[IEEE Journal of Solid-State Circuits (JSSC)](https://ieeexplore.ieee.org/document/8959403)

JSSC 2020 Best Paper award

### 2019

[MAGNet: A Modular Accelerator Generator for Neural Networks](/publication/2019-11_magnet-modular-accelerator-generator-neural-networks)

[Rangharajan Venkatesan](/person/rangharajan-venkatesan), Sophia Shao, Miaorong Wang, [Jason Clemons](/person/jason-clemons), [Steve Dai](/person/steve-dai), [Matt Fojtik](/person/matt-fojtik), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Yanqing Zhang](/person/yanqing-zhang), [Brian Zimmer](/person/brian-zimmer), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Steve Keckler](/person/stephen-keckler), [Brucek Khailany](/person/brucek-khailany)

[International Conference On Computer Aided Design (ICCAD)](https://ieeexplore.ieee.org/document/8942127)

[Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture](/publication/2019-10_simba-scaling-deep-learning-inference-multi-chip-module-based-architecture)

Sophia Shao, [Jason Clemons](/person/jason-clemons), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Brian Zimmer](/person/brian-zimmer), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Brucek Khailany](/person/brucek-khailany), [Steve Keckler](/person/stephen-keckler)

[International Symposium on Microarchitecture (MICRO)](https://dl.acm.org/doi/10.1145/3352460.3358302)

Best Paper award, IEEE Micro Top Picks in Computer Architecture (Honorable Mention)

[A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator Designed with a High-Productivity VLSI Methodology](/publication/2019-08_011-pjop-032-128-tops-scalable-multi-chip-module-based-deep-neural-network)

[Rangharajan Venkatesan](/person/rangharajan-venkatesan), Sophia Shao, [Brian Zimmer](/person/brian-zimmer), [Jason Clemons](/person/jason-clemons), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Steve Keckler](/person/stephen-keckler), [Brucek Khailany](/person/brucek-khailany)

[Hot Chips: A Symposium on High Performance Chips](http://www.hotchips.org/)

[A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm](/publication/2019-06_011-pjop-032-128-tops-scalable-multi-chip-module-based-deep-neural-network)

[Brian Zimmer](/person/brian-zimmer), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), Sophia Shao, [Jason Clemons](/person/jason-clemons), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Steve Keckler](/person/stephen-keckler), [Brucek Khailany](/person/brucek-khailany)

[Symposium on VLSI Circuits](https://ieeexplore.ieee.org/document/8778056)

[A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET](/publication/2019-05_fine-grained-gals-soc-pausible-adaptive-clocking-16-nm-finfet)

[Matt Fojtik](/person/matt-fojtik), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), [Stephen Tell](/person/stephen-tell), [Brian Zimmer](/person/brian-zimmer), Tezaswi Raja, Kevin Zhou, [William Dally](/person/william-dally), [Brucek Khailany](/person/brucek-khailany)

[ASYNC 2019](http://www.async2019.jp/)

ASYNC 2019 Best Paper Award

### 2018

[A Modular Digital VLSI Flow for High-Productivity SoC Design](/index.php/publication/2018-06_modular-digital-vlsi-flow-high-productivity-soc-design)

[Brucek Khailany](/index.php/person/brucek-khailany), Evgeni Krimer, [Rangharajan Venkatesan](/index.php/person/rangharajan-venkatesan), [Jason Clemons](/index.php/person/jason-clemons), [Joel Emer](/index.php/person/joel-emer), [Matt Fojtik](/index.php/person/matt-fojtik), Alicia Klinefelter, [Michael Pellauer](/index.php/person/michael-pellauer), [Nathaniel Pinckney](/index.php/person/nathaniel-pinckney), Sophia Shao, Shreesha Srinath, Christopher Torng, Sam (Likun) Xi, [Yanqing Zhang](/index.php/person/yanqing-zhang), [Brian Zimmer](/index.php/person/brian-zimmer)

[Design Automation Conference (DAC)](https://dl.acm.org/doi/10.1145/3195970.3199846)

[Ground-Referenced Signaling for Intra-Chip and Short-Reach Chip-to-Chip Interconnects](/publication/2018-04_ground-referenced-signaling-intra-chip-and-short-reach-chip-chip-interconnects)

[Walker Turner](/person/walker-turner), John Poulton, [John Wilson](/person/john-wilson), [Xi Chen](/person/xi-chen), [Stephen Tell](/person/stephen-tell), [Matt Fojtik](/person/matt-fojtik), [Trey Greer](/person/trey-greer), [Brian Zimmer](/person/brian-zimmer), [Sanquan Song](/person/sanquan-song), [Nikola Nedovic](/person/nikola-nedovic), [Sudhir Kudva](/person/sudhir-kudva), Sunil Sudhakaran, Rizwan Bashirullah, Wenxu Zhao, [William Dally](/person/william-dally), [Tom Gray](/person/tom-gray)

Custom Integrated Circuits Conference

### 2016

[Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks](/index.php/publication/2016-05_modeling-and-analysis-power-supply-noise-tolerance-fine-grained-gals-adaptive)

Divya Akella Kamakshi, [Matt Fojtik](/index.php/person/matt-fojtik), [Brucek Khailany](/index.php/person/brucek-khailany), [Sudhir Kudva](/index.php/person/sudhir-kudva), Yaping Zhou, Benton H. Calhoun

[ASYNC 2016](http://www.inf.pucrs.br/async2016/)

ASYNC 2016 Best Paper Award Nominee

[A 28nm 2Mbit 6T SRAM with Highly Configurable Write Assist Implementation and Capacitor Based Sense Amplifier Input Offset Compen](/publication/2016-02_28nm-2mbit-6t-sram-highly-configurable-write-assist-implementation-and)

Mahmut Sinangil, John Poulton, [Matt Fojtik](/person/matt-fojtik), [Trey Greer](/person/trey-greer), [Stephen Tell](/person/stephen-tell), Andy Gotterba, Jesse Wang, Jason Golbus, [William Dally](/person/william-dally), [Tom Gray](/person/tom-gray)

Journal of Solid State Circuits

[A 6.5-to-23.3fJ/b/mm Balanced Charge-Recycling Bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with Clock Forwarding and Low-Crosstalk Contraflow Wiring](/publication/2016-02_65-233fjbmm-balanced-charge-recycling-bus-16nm-finfet-cmos-17-26gbswire-clock)

[John Wilson](/person/john-wilson), [Matt Fojtik](/person/matt-fojtik), John Poulton, [Xi Chen](/person/xi-chen), [Stephen Tell](/person/stephen-tell), [Trey Greer](/person/trey-greer), [Tom Gray](/person/tom-gray), [William Dally](/person/william-dally)

[International Solid-State Circuits Conference (ISSCC 2016)](http://ieeexplore.ieee.org/document/7417954/)

### 2015

[A Pausible Bisynchronous FIFO for GALS Systems](/index.php/publication/2015-05_pausible-bisynchronous-fifo-gals-systems)

Ben Keller, [Matt Fojtik](/index.php/person/matt-fojtik), [Brucek Khailany](/index.php/person/brucek-khailany)

[ASYNC 2015](http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7152683&tag=1)