Nathaniel Pinckney ![](/sites/default/files/person/nathaniel-pinckney.jpg) Nathaniel Pinckney received his PhD from David Blaauw’s research group at the University of Michigan in 2015. His research focused on near-threshold characterization of planar and FinFET devices, and fast voltage boosting. Prior to UM he worked for two years in Sun Microsystems’ VLSI Research group (presently Oracle Labs). His undergraduate degree is from Harvey Mudd College, where he was advised by David Money Harris. Research Area(s) [Computer Architecture](/research-area/computer-architecture) [Artificial Intelligence and Machine Learning ](/research-area/machine-learning-artificial-intelligence) Main Field of Interest [Circuits and VLSI Design](/research-area/circuits) Google Scholar [https://scholar.google.com/citations?user=v4Nb6ooAAAAJ&hl=en](https://scholar.google.com/citations?user=v4Nb6ooAAAAJ&hl=en) ### Publications ### 2026 [Alpha-Vision: A Real-Time Always-on Vision Processor with 787µs Face Detection Latency in <5mW](/publication/2026-02_alpha-vision-real-time-always-vision-processor-787ms-face-detection-latency) [Ben Keller](/person/ben-keller), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Steve Dai](/person/steve-dai), [Jason Clemons](/person/jason-clemons), [Matt Fojtik](/person/matt-fojtik), [Muya Chang](/person/muya-chang), Thierry Tambe, [Nathaniel Pinckney](/person/nathaniel-pinckney), [Stephen Tell](/person/stephen-tell), [Qijing Jenny Huang](/person/qijing-jenny-huang), [Shalini De Mello](/person/shalini-de-mello), [Brucek Khailany](/person/brucek-khailany) [ISSCC 2026](https://www.isscc.org/) ### 2023 [ChipNeMo: Domain-Adapted LLMs for Chip Design](/publication/2023-10_chipnemo-domain-adapted-llms-chip-design) [Mingjie Liu](/person/mingjie-liu), Teo Ene, Robert Kirby, Chris Cheng, [Nathaniel Pinckney](/person/nathaniel-pinckney), [Rongjian Liang](/person/rongjian-liang), Jonah Alben, Himyanshu Anand, Sanmitra Banerjee, Ismet Bayraktaroglu, Bonita Bhaskaran, Bryan Catanzaro, Arjun Chaudhuri, Sharon Clay, Bill Dally, Laura Dang, Parikshit Deshpande, Siddhanth Dhodhi, Sameer Halepete, Eric Hill, Jiashang Hu, Sumit Jain, [Brucek Khailany](/person/brucek-khailany), George Kokai, Kishor Kunal, Xiaowei Li, Charley Lind, Hao Liu, Stuart Oberman, Sujeet Omar, Sreedhar Pratty, Jonathan Raman, Ambar Sarkar, Zhengjiang Shao, Hanfei Sun, Pratik P Suthar, Varun Tej, [Walker Turner](/person/walker-turner), Kaizhe Xu, Mark Haoxing Ren [VerilogEval: Evaluating Large Language Models for Verilog Code Generation](/publication/2023-09_verilogeval-evaluating-large-language-models-verilog-code-generation) [Mingjie Liu](/person/mingjie-liu), [Nathaniel Pinckney](/person/nathaniel-pinckney), [Brucek Khailany](/person/brucek-khailany), Mark Haoxing Ren [2023 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)](https://arxiv.org/abs/2309.07544) [Late Breaking Results: Test Selection For RTL Coverage By Unsupervised Learning From Fast Functional Simulation](/publication/2023-07_late-breaking-results-test-selection-rtl-coverage-unsupervised-learning-fast) [Rongjian Liang](/person/rongjian-liang), [Nathaniel Pinckney](/person/nathaniel-pinckney), Yuji Chai, Mark Haoxing Ren, [Brucek Khailany](/person/brucek-khailany) [60th Design Automation Conference](https://www.dac.com/) ### 2021 [IPA: Floorplan-Aware SystemC Interconnect Performance Modeling and Generation for HLS-based SoCs](/index.php/publication/2021-11_ipa-floorplan-aware-systemc-interconnect-performance-modeling-and-generation) [Nathaniel Pinckney](/index.php/person/nathaniel-pinckney), [Rangharajan Venkatesan](/index.php/person/rangharajan-venkatesan), [Ben Keller](/index.php/person/ben-keller), [Brucek Khailany](/index.php/person/brucek-khailany) [IEEE/ACM International Conference on Computer-Aided Design (ICCAD ’21)](https://iccad.com/) [Simba: scaling deep-learning inference with chiplet-based architecture](/publication/2021-05_simba-scaling-deep-learning-inference-chiplet-based-architecture) Yakun Sophia Shao, [Jason Clemons](/person/jason-clemons), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Brian Zimmer](/person/brian-zimmer), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Brucek Khailany](/person/brucek-khailany), [Steve Keckler](/person/stephen-keckler) [Communications of the ACM](https://dl.acm.org/doi/10.1145/3460227) ACM Research Highlight [Verifying High-Level Latency-Insensitive Designs with Formal Model Checking](/index.php/publication/2021-02_verifying-high-level-latency-insensitive-designs-formal-model-checking) [Steve Dai](/index.php/person/steve-dai), Alicia Klinefelter, Mark Haoxing Ren, [Rangharajan Venkatesan](/index.php/person/rangharajan-venkatesan), [Ben Keller](/index.php/person/ben-keller), [Nathaniel Pinckney](/index.php/person/nathaniel-pinckney), [Brucek Khailany](/index.php/person/brucek-khailany) [arXiv](https://arxiv.org/abs/2102.06326) ### 2020 [A 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm](/publication/2020-01_032-128-tops-scalable-multi-chip-module-based-deep-neural-network-inference) [Brian Zimmer](/person/brian-zimmer), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), Yakun Sophia Shao, [Jason Clemons](/person/jason-clemons), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Steve Keckler](/person/stephen-keckler), [Brucek Khailany](/person/brucek-khailany) [IEEE Journal of Solid-State Circuits (JSSC)](https://ieeexplore.ieee.org/document/8959403) JSSC 2020 Best Paper award ### 2019 [MAGNet: A Modular Accelerator Generator for Neural Networks](/publication/2019-11_magnet-modular-accelerator-generator-neural-networks) [Rangharajan Venkatesan](/person/rangharajan-venkatesan), Sophia Shao, Miaorong Wang, [Jason Clemons](/person/jason-clemons), [Steve Dai](/person/steve-dai), [Matt Fojtik](/person/matt-fojtik), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Yanqing Zhang](/person/yanqing-zhang), [Brian Zimmer](/person/brian-zimmer), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Steve Keckler](/person/stephen-keckler), [Brucek Khailany](/person/brucek-khailany) [International Conference On Computer Aided Design (ICCAD)](https://ieeexplore.ieee.org/document/8942127) [Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture](/publication/2019-10_simba-scaling-deep-learning-inference-multi-chip-module-based-architecture) Sophia Shao, [Jason Clemons](/person/jason-clemons), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Brian Zimmer](/person/brian-zimmer), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Brucek Khailany](/person/brucek-khailany), [Steve Keckler](/person/stephen-keckler) [International Symposium on Microarchitecture (MICRO)](https://dl.acm.org/doi/10.1145/3352460.3358302) Best Paper award, IEEE Micro Top Picks in Computer Architecture (Honorable Mention) [A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator Designed with a High-Productivity VLSI Methodology](/publication/2019-08_011-pjop-032-128-tops-scalable-multi-chip-module-based-deep-neural-network) [Rangharajan Venkatesan](/person/rangharajan-venkatesan), Sophia Shao, [Brian Zimmer](/person/brian-zimmer), [Jason Clemons](/person/jason-clemons), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Steve Keckler](/person/stephen-keckler), [Brucek Khailany](/person/brucek-khailany) [Hot Chips: A Symposium on High Performance Chips](http://www.hotchips.org/) [A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm](/publication/2019-06_011-pjop-032-128-tops-scalable-multi-chip-module-based-deep-neural-network) [Brian Zimmer](/person/brian-zimmer), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), Sophia Shao, [Jason Clemons](/person/jason-clemons), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Steve Keckler](/person/stephen-keckler), [Brucek Khailany](/person/brucek-khailany) [Symposium on VLSI Circuits](https://ieeexplore.ieee.org/document/8778056) [A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET](/publication/2019-05_fine-grained-gals-soc-pausible-adaptive-clocking-16-nm-finfet) [Matt Fojtik](/person/matt-fojtik), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), [Stephen Tell](/person/stephen-tell), [Brian Zimmer](/person/brian-zimmer), Tezaswi Raja, Kevin Zhou, [William Dally](/person/william-dally), [Brucek Khailany](/person/brucek-khailany) [ASYNC 2019](http://www.async2019.jp/) ASYNC 2019 Best Paper Award ### 2018 [A Modular Digital VLSI Flow for High-Productivity SoC Design](/index.php/publication/2018-06_modular-digital-vlsi-flow-high-productivity-soc-design) [Brucek Khailany](/index.php/person/brucek-khailany), Evgeni Krimer, [Rangharajan Venkatesan](/index.php/person/rangharajan-venkatesan), [Jason Clemons](/index.php/person/jason-clemons), [Joel Emer](/index.php/person/joel-emer), [Matt Fojtik](/index.php/person/matt-fojtik), Alicia Klinefelter, [Michael Pellauer](/index.php/person/michael-pellauer), [Nathaniel Pinckney](/index.php/person/nathaniel-pinckney), Sophia Shao, Shreesha Srinath, Christopher Torng, Sam (Likun) Xi, [Yanqing Zhang](/index.php/person/yanqing-zhang), [Brian Zimmer](/index.php/person/brian-zimmer) [Design Automation Conference (DAC)](https://dl.acm.org/doi/10.1145/3195970.3199846)