Ted Jiang ![](/sites/default/files/person/nan%2520%2528ted%2529-jiang.jpg) Ted Jiang joined NVIDIA research at the end of 2012 after completing his PhD in electrical engineering at Stanford University. His research interests span a wide range of interconnection networks topics from routing algorithms, congestion control mechanisms, allocator designs, router designs, topology analysis, and network simulation. His network expertise spans from network-on-chip for SoC or CMP systems to large scale system area networks for high performance computing and Datacenters. Research Area(s) [High Performance Computing](/research-area/high-performance-computing) [Networking](/research-area/networking) Google Scholar [https://scholar.google.com/citations?user=NrVDLbgAAAAJ&hl=en](https://scholar.google.com/citations?user=NrVDLbgAAAAJ&hl=en) ### Publications ### 2021 [Simba: scaling deep-learning inference with chiplet-based architecture](/publication/2021-05_simba-scaling-deep-learning-inference-chiplet-based-architecture) Yakun Sophia Shao, [Jason Clemons](/person/jason-clemons), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Brian Zimmer](/person/brian-zimmer), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Brucek Khailany](/person/brucek-khailany), [Steve Keckler](/person/stephen-keckler) [Communications of the ACM](https://dl.acm.org/doi/10.1145/3460227) ACM Research Highlight [Need for Speed: Experiences Building a Trustworthy System-Level GPU Simulator.](/publication/2021-02_need-speed-experiences-building-trustworthy-system-level-gpu-simulator) Oreste Villa, [Daniel Lustig](/person/daniel-lustig), [Zi Yan](/person/zi-yan), Evgeny Bolotin, [Yaosheng Fu](/person/yaosheng-fu), [Niladrish Chatterjee](/person/niladrish-chatterjee), [Ted Jiang](/person/ted-jiang), [David Nellans](/person/david-nellans) [International Symposium on High Performance Computer Architecture (HPCA)](https://doi.org/10.1109/HPCA51647.2021.00077) ### 2020 [An In-Network Architecture for Accelerating Shared-Memory Multiprocessor Collectives](/publication/2020-05_network-architecture-accelerating-shared-memory-multiprocessor-collectives) [Benjamin Klenk](/person/ben-klenk), [Ted Jiang](/person/ted-jiang), Greg Thorson, [Larry Dennison](/person/larry-dennison) [International Symposium on Computer Architecture (ISCA)](https://dl.acm.org/doi/10.1109/ISCA45697.2020.00085) [A 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm](/publication/2020-01_032-128-tops-scalable-multi-chip-module-based-deep-neural-network-inference) [Brian Zimmer](/person/brian-zimmer), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), Yakun Sophia Shao, [Jason Clemons](/person/jason-clemons), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Steve Keckler](/person/stephen-keckler), [Brucek Khailany](/person/brucek-khailany) [IEEE Journal of Solid-State Circuits (JSSC)](https://ieeexplore.ieee.org/document/8959403) JSSC 2020 Best Paper award ### 2019 [Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture](/publication/2019-10_simba-scaling-deep-learning-inference-multi-chip-module-based-architecture) Sophia Shao, [Jason Clemons](/person/jason-clemons), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), [Brian Zimmer](/person/brian-zimmer), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Brucek Khailany](/person/brucek-khailany), [Steve Keckler](/person/stephen-keckler) [International Symposium on Microarchitecture (MICRO)](https://dl.acm.org/doi/10.1145/3352460.3358302) Best Paper award, IEEE Micro Top Picks in Computer Architecture (Honorable Mention) [A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator Designed with a High-Productivity VLSI Methodology](/publication/2019-08_011-pjop-032-128-tops-scalable-multi-chip-module-based-deep-neural-network) [Rangharajan Venkatesan](/person/rangharajan-venkatesan), Sophia Shao, [Brian Zimmer](/person/brian-zimmer), [Jason Clemons](/person/jason-clemons), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Steve Keckler](/person/stephen-keckler), [Brucek Khailany](/person/brucek-khailany) [Hot Chips: A Symposium on High Performance Chips](http://www.hotchips.org/) [A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm](/publication/2019-06_011-pjop-032-128-tops-scalable-multi-chip-module-based-deep-neural-network) [Brian Zimmer](/person/brian-zimmer), [Rangharajan Venkatesan](/person/rangharajan-venkatesan), Sophia Shao, [Jason Clemons](/person/jason-clemons), [Matt Fojtik](/person/matt-fojtik), [Ted Jiang](/person/ted-jiang), [Ben Keller](/person/ben-keller), Alicia Klinefelter, [Nathaniel Pinckney](/person/nathaniel-pinckney), Priyanka Raina, [Stephen Tell](/person/stephen-tell), [Yanqing Zhang](/person/yanqing-zhang), [William Dally](/person/william-dally), [Joel Emer](/person/joel-emer), [Tom Gray](/person/tom-gray), [Steve Keckler](/person/stephen-keckler), [Brucek Khailany](/person/brucek-khailany) [Symposium on VLSI Circuits](https://ieeexplore.ieee.org/document/8778056) ### 2018 [Exploiting Idle Resources in a High-Radix Switch for Supplemental Storage](/publication/2018-11_exploiting-idle-resources-high-radix-switch-supplemental-storage) [Matthias Blumrich](/person/matthias-blumrich), [Ted Jiang](/person/ted-jiang), [Larry Dennison](/person/larry-dennison) [Proceedings of the International Conference for High Performance Computing, Net…](https://dl.acm.org/citation.cfm?id=3291662) ### 2015 [Network Endpoint Congestion Control for Fine-Grained Communication](/publication/2015-11_network-endpoint-congestion-control-fine-grained-communication) [Ted Jiang](/person/ted-jiang), [Larry Dennison](/person/larry-dennison), [William Dally](/person/william-dally) [SC15](http://dl.acm.org/citation.cfm?id=2807600)