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2. A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS
 
 # A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS

  ![](/sites/default/files/styles/wide/public/pubs/2007-12_A-14-mW-6/SolidStateCircuits.jpg?itok=su5n5dcQ)

 This paper describes a 6.25-Gb/s 14-mW transceiver in 90-nm CMOS for chip-to-chip applications. The transceiver employs a number of features for reducing power consumption, including a shared LC-PLL clock multiplier, an inductor-loaded resonant clock distribution network, a low- and programmable-swing voltage-mode transmitter, software-controlled clock and data recovery (CDR) and adaptive equalization within the receiver, and a novel PLL-based phase rotator for the CDR. The design can operate with channel attenuation of -15 dB or greater at a bit-error rate of 10-15 or less, while consuming less than 2.25 mW/Gb/s per transceiver.



 ## Authors



John Poulton (NVIDIA)

Robert Palmer (NVIDIA)

Andy Fuller (Duke University)

[Trey Greer](/person/trey-greer)

John Eyles (NVIDIA)

[William Dally](/person/william-dally)

Mark Horowitz (Stanford)

 

 

 ## Publication Date



Saturday, December 1, 2007

 

 ## Published in



[IEEE Journal of Solid-State Circuits](http://www.ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=4)

 

 ## Research Area



[Circuits and VLSI Design](/research-area/circuits)

 

 

 ## Copyright



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