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2. Scaling the Power Wall: A Path to Exascale
 
 # Scaling the Power Wall: A Path to Exascale

  ![](/sites/default/files/styles/wide/public/publications/villa.sc2014_0.png?itok=marN_HxM)

 Modern scientific discovery is driven by an insatiable demand for computing performance. The HPC community is targeting development of supercomputers able to sustain 1 ExaFlops by the year 2020 and power consumption is the primary obstacle to achieving this goal. A combination of architectural improvements, circuit design, and manufacturing technologies must provide over a 20× improvement in energy efficiency. In this paper, we present some of the progress NVIDIA is making toward the design of Exascale systems by tailoring features to address the scaling challenges of performance and energy efficiency. We evaluate several architectural concepts for a set of HPC applications demonstrating expected energy efficiency improvements resulting from circuit and packaging innovations such as low-voltage SRAM, low-energy signaling, and on-package memory. Finally, we discuss the scaling of these features with respect to future process technologies and provide power and performance projections for our Exascale research architecture.



 ## Authors



Oreste Villa (NVIDIA)

Daniel Johnson (NVIDIA)

[Mike O'Connor](/person/mike-o-connor)

Evgeny Bolotin (NVIDIA)

[David Nellans](/person/david-nellans)

Justin Luitjens (NVIDIA)

Nikolai Sakharnykh (NVIDIA)

Peng Wang (NVIDIA)

Paulius Micikevicius (NVIDIA)

Anthony Scudiero (NVIDIA)

[Steve Keckler](/person/stephen-keckler)

[William Dally](/person/william-dally)

 

 

 ## Publication Date



Sunday, November 16, 2014

 

 ## Published in



[SC '14](http://ieeexplore.ieee.org/abstract/document/7013055/)

 

 ## Research Area



[Computer Architecture](/research-area/computer-architecture)

[High Performance Computing](/research-area/high-performance-computing)

 

 

 ## External Links



[IEEE Digital Library](http://ieeexplore.ieee.org/abstract/document/7013055/)

 

 

 ## Uploaded Files



[Published manuscript](https://research.nvidia.com/sites/default/files/pubs/2014-11_Scaling-the-Power//villa.sc2014.pdf "Open file in new window")603.37 KB

 

 

 ## Copyright



This material is posted here with permission of the IEEE. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to <pubs-permissions@ieee.org>.