1. [Publications](/publications)
2. High-speed Low-power On-chip Global Signaling Design Overview
 
 # High-speed Low-power On-chip Global Signaling Design Overview

  ![](/sites/default/files/styles/wide/public/pubs/2015-01_High-speed-Low-power-On-chip/default.jpg?itok=gqlQaxjt)

 On-chip global signaling in modern SoCs faces significant challenges due to wire pitch scaling and increasing die size. Conventional on-chip synchronous CMOS links have already hit a performance wall in power and latency. Although approaches based on custom low-swing equalized serial-link techniques can yield improvements, strict power/silicon budgets and non-ideal in-situ conditions of large SoCs make their design much more challenging than simply transitioning off-chip signaling technologies to onchip. Therefore, a holistic approach to the on-chip global signaling problem is required. We present analyses and solutions that take into account channel design, low power transceiver circuits, clocking architectures, and power supply considerations.



 ## Authors



[Xi Chen](/person/xi-chen)

[John Wilson](/person/john-wilson)

John Poulton (NVIDIA)

Rizwan Bashirullah (NVIDIA)

[Tom Gray](/person/tom-gray)

 

 

 ## Publication Date



Thursday, January 29, 2015

 

 ## Published in



[DesignCon](http://presentations.designcon.com/events/santa-clara/2015/conference-sessions)

 

 ## Research Area



[Circuits and VLSI Design](/research-area/circuits)

 

 

 ## Uploaded Files



[1-TH5Paper\_High-speedLow-powerOn-chipGlobalSignaling .pdf](https://research.nvidia.com/sites/default/files/publications/1-TH5Paper_High-speedLow-powerOn-chipGlobalSignaling%20.pdf "Open file in new window")1.06 MB

[1-TH5Slides\_High-speedLow-powerOn-chipGlobalSignaling.pdf](https://research.nvidia.com/sites/default/files/publications/1-TH5Slides_High-speedLow-powerOn-chipGlobalSignaling.pdf "Open file in new window")1.49 MB