1. [Publications](/publications) 2. A 28nm 2Mbit 6T SRAM with Highly Configurable Write Assist Implementation and Capacitor Based Sense Amplifier Input Offset Compen # A 28nm 2Mbit 6T SRAM with Highly Configurable Write Assist Implementation and Capacitor Based Sense Amplifier Input Offset Compen ![](/sites/default/files/styles/wide/public/pubs/2016-02_A-28nm-2Mbit/default.jpg?itok=bQH8bzMF) ## Authors Mahmut Sinangil (NVIDIA) John Poulton (NVIDIA) [Matt Fojtik](/person/matt-fojtik) [Trey Greer](/person/trey-greer) [Stephen Tell](/person/stephen-tell) Andy Gotterba (NVIDIA) Jesse Wang (NVIDIA) Jason Golbus (NVIDIA) [William Dally](/person/william-dally) [Tom Gray](/person/tom-gray) ## Publication Date Monday, February 1, 2016 ## Published in Journal of Solid State Circuits ## Research Area [Circuits and VLSI Design](/research-area/circuits) ## Copyright This material is posted here with permission of the IEEE. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to .