1. [Publications](/publications) 2. An Analytical Model for Hardened Latch Selection and Exploration # An Analytical Model for Hardened Latch Selection and Exploration ![](/sites/default/files/styles/wide/public/publications/analytical_ff.JPG?itok=YHyGinjC) Hardened flip-flops and latches are designed to be resilient to soft errors, maintaining high system reliability in the presence of energetic radiation. The wealth of different hardened designs (with varying protection levels) and the probabilistic nature of reliability complicates the choice of which hardened storage element to substitute where. This paper develops an analytical model for hardened latch and flip-flop design space exploration. It is shown that the best hardened design depends strongly on the target protection level and the chip that is being protected. Also, the use of multiple complementary hardened cells can combine the relative advantages of each design, garnering significant efficiency improvements in many situations. ## Authors [Michael B. Sullivan](/person/mike-sullivan) [Brian Zimmer](/person/brian-zimmer) [Siva Hari](/person/siva-hari) Timothy Tsai (NVIDIA) [Steve Keckler](/person/stephen-keckler) ## Publication Date Tuesday, March 1, 2016 ## Published in [Workshop on Silicon Errors in Logic--System Effects (SELSE)](http://www.selse.org/) ## Research Area [Computer Architecture](/research-area/computer-architecture) ## Uploaded Files [Published manuscript](https://d1qx31qr3h6wln.cloudfront.net/publications/SELSE_2016_Hardened_Latch_Model.pdf "Open file in new window")785.52 KB ## Copyright This material is posted here with permission of the IEEE. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to .