1. [Publications](/publications) 2. DUCATI: High-performance Address Translation by Extending TLB Reach of GPU-accelerated Systems # DUCATI: High-performance Address Translation by Extending TLB Reach of GPU-accelerated Systems ![Publication image](/sites/default/files/styles/wide/public/default_images/default.jpeg?itok=qUFsuJCP "Publication image") Conventional on-chip TLB hierarchies are unable to fully cover the growing application working-set sizes. To make things worse, Last-Level TLB (LLT) misses require multiple accesses to the page table even with the use of page walk caches. Consequently, LLT misses incur long address translation latency and hurt performance. This paper proposes two low-overhead hardware mechanisms for reducing the frequency and penalty of on-die LLT misses. The first, Unified CAche and TLB (UCAT), enables the conventional on-die Last-Level Cache (LLC) to store cache lines and TLB entries in a single unified structure and increases ondie TLB capacity significantly. The second, DRAM-TLB, memoizes virtual to physical address translations in DRAM and reduces LLT miss penalty when UCAT is unable to fully cover total application working-set. DRAM-TLB serves as the next larger level in the TLB hierarchy that significantly increases TLB coverage relative to on-chip TLBs. The combination of these two mechanisms, DUCATI, is an address translation architecture that improves GPU performance by 81% (up to 4.5x) while requiring minimal changes to the existing system design. We show that DUCATI is within 20%, 5%, and 2% the performance of a perfect LLT system when using 4KB, 64KB, and 2MB pages respectively. ## Authors [Aamer Jaleel](/person/aamer-jaleel) Eiman Ebrahimi (NVIDIA) Sam Duncan (NVIDIA) ## Publication Date Friday, March 8, 2019 ## Published in [ACM Transactions on Architecture and Code Optimization (TACO)](https://dl.acm.org/doi/abs/10.1145/3309710) ## Research Area [Computer Architecture](/research-area/computer-architecture) ## External Links [Published manuscript (ACM Digital Library)](https://dl.acm.org/doi/abs/10.1145/3309710) ## Copyright Copyright by the Association for Computing Machinery, Inc. Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, to republish, to post on servers, or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from Publications Dept, ACM Inc., fax +1 (212) 869-0481, or . The definitive version of this paper can be found at ACM's Digital Library .