1. [Publications](/publications)
2. A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm
 
 # A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm

  ![](/sites/default/files/styles/wide/public/publications/RC18_photo_0.jpg?itok=W672v7dA)

 This work presents a scalable deep neural network (DNN) accelerator consisting of 36 chips connected in a mesh network on a multi-chip-module (MCM) using ground-referenced signaling (GRS). While previous accelerators fabricated on a single monolithic die are limited to specific network sizes, the proposed architecture enables flexible scaling for efficient inference on a wide range of DNNs, from mobile to data center domains. The 16nm prototype achieves 1.29 TOPS/mm^2, 0.11 pJ/op energy efficiency, 4.01 TOPS peak performance for a 1-chip system, and 127.8 peak TOPS and 2615 images/s ResNet-50 inference for a 36-chip system.



 ## Authors



[Brian Zimmer](/person/brian-zimmer)

[Rangharajan Venkatesan](/person/rangharajan-venkatesan)

Sophia Shao (NVIDIA)

[Jason Clemons](/person/jason-clemons)

[Matt Fojtik](/person/matt-fojtik)

[Ted Jiang](/person/ted-jiang)

[Ben Keller](/person/ben-keller)

Alicia Klinefelter (NVIDIA)

[Nathaniel Pinckney](/person/nathaniel-pinckney)

Priyanka Raina (Stanford University)

[Stephen Tell](/person/stephen-tell)

[Yanqing Zhang](/person/yanqing-zhang)

[William Dally](/person/william-dally)

[Joel Emer](/person/joel-emer)

[Tom Gray](/person/tom-gray)

[Steve Keckler](/person/stephen-keckler)

[Brucek Khailany](/person/brucek-khailany)

 

 

 ## Publication Date



Sunday, June 9, 2019

 

 ## Published in



[Symposium on VLSI Circuits](https://ieeexplore.ieee.org/document/8778056)

 

 ## Research Area



[Artificial Intelligence and Machine Learning ](/research-area/machine-learning-artificial-intelligence)

[Circuits and VLSI Design](/research-area/circuits)

 

 

 ## External Links



[IEEE Digital Library](https://ieeexplore.ieee.org/document/8778056)

 

 

 ## Uploaded Files



[Published manuscriptshed](https://d1qx31qr3h6wln.cloudfront.net/publications/VLSI_2019_InferenceChip.pdf "Open file in new window")525.33 KB

 

 

 ## Copyright



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