1. [Publications](/publications)
2. ABCDPlace: Accelerated Batch-based Concurrent Detailed Placement on Multi-threaded CPUs and GPUs
 
 # ABCDPlace: Accelerated Batch-based Concurrent Detailed Placement on Multi-threaded CPUs and GPUs

  ![Publication image](/sites/default/files/styles/wide/public/default_images/default.jpeg?itok=qUFsuJCP "Publication image")

 Placement is an important step in modern very-large-scale integrated (VLSI) designs. Detailed placement is a placement refining procedure intensively called throughout the design flow, thus its efficiency has a vital impact on design closure. However, since most detailed placement techniques are inherently greedy and sequential, they are generally difficult to parallelize. In this work, we present a concurrent detailed placement framework, ABCDPlace, exploiting multithreading and GPU acceleration. We propose batch-based concurrent algorithms for widely-adopted sequential detailed placement techniques, such as independent set matching, global swap, and local reordering. Experimental results demonstrate that ABCDPlace can achieve 2×-5× faster runtime than sequential implementations with multi-threaded CPU and over 10× with GPU on ISPD 2005 contest benchmarks without quality degradation. On larger industrial benchmarks, we show more than 16× speedup with GPU over the state-of-the-art sequential detailed placer. ABCDPlace finishes the detailed placement of a 10-million-cell industrial design in one minute.



 ## Authors



Yibo Lin (Peking University)

Wuxi Li (Xilinx)

Jiaqi Gu (UT-Austin)

Mark Haoxing Ren (NVIDIA)

[Brucek Khailany](/person/brucek-khailany)

David Z. Pan (UT-Austin)

 

 

 ## Publication Date



Tuesday, February 4, 2020

 

 ## Published in



[IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (…](https://ieeexplore.ieee.org/document/8982049)

 

 ## Research Area



[Algorithms and Numerical Methods](/research-area/algorithms)

[Circuits and VLSI Design](/research-area/circuits)

 

 

 ## Copyright



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