1. [Publications](/publications)
2. Accelerating Chip Design with Machine Learning
 
 # Accelerating Chip Design with Machine Learning

  ![](/sites/default/files/styles/wide/public/publications/khailany-fig4.cropped.jpg?itok=etc6FMsI)

 Recent advancements in machine learning provide an opportunity to transform chip design workflows. We review recent research applying techniques such as deep convolutional neural networks and graph-based neural networks in the areas of automatic design space exploration, power analysis, VLSI physical design, and analog design. We also present a future vision of an AI-assisted automated chip design workflow to aid designer productivity and automate optimization tasks.



 ## Authors



[Brucek Khailany](/person/brucek-khailany)

Mark Haoxing Ren (NVIDIA)

[Steve Dai](/person/steve-dai)

Saad Godil (NVIDIA)

[Ben Keller](/person/ben-keller)

Robert Kirby (NVIDIA)

Alicia Klinefelter (NVIDIA)

[Rangharajan Venkatesan](/person/rangharajan-venkatesan)

[Yanqing Zhang](/person/yanqing-zhang)

Bryan Catanzaro (NVIDIA)

[William Dally](/person/william-dally)

 

 

 ## Publication Date



Thursday, September 24, 2020

 

 ## Published in



[IEEE Micro](https://ieeexplore.ieee.org/document/9205654)

 

 ## Research Area



[Circuits and VLSI Design](/research-area/circuits)

[Artificial Intelligence and Machine Learning ](/research-area/machine-learning-artificial-intelligence)

 

 

 ## Copyright



This material is posted here with permission of the IEEE. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to <pubs-permissions@ieee.org>.