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2. A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS
 
 # A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS

  ![](/sites/default/files/styles/wide/public/publications/ISR_JSSC_0.jpg?itok=YkdYVZcN)

 This article presents a clock-forwarded, inverter-based short-reach simultaneous bi-directional (ISR-SBD) physical layer (PHY) targeted for die-to-die communication over silicon interposers or similar high-density interconnect. Short-reach links of this type are increasingly important to support larger systems built with chiplets and multiple die and to facilitate the shift to medium- and long-range optical communication based on silicon photonics. This project explores the advantages of simultaneous bi-directional signaling (SBD) over other bandwidth-doubling techniques (e.g., PAM4). Fabricated in a 5-nm standard CMOS process, the ISR-SBD PHY demonstrates 50.4 Gb/s/wire (25.2 Gb/s each direction) and 0.297 pJ/bit on a 750-mV supply over a 1.2-mm on- chip channel.



 ## Authors



[Yoshinori Nishi](/person/yoshi-nishi)

John W. Poulton (NVIDIA)

[Walker Turner](/person/walker-turner)

[Xi Chen](/person/xi-chen)

[Sanquan Song](/person/sanquan-song)

[Brian Zimmer](/person/brian-zimmer)

[Stephen Tell](/person/stephen-tell)

[Nikola Nedovic](/person/nikola-nedovic)

[John Wilson](/person/john-wilson)

[William Dally](/person/william-dally)

[Tom Gray](/person/tom-gray)

 

 

 ## Publication Date



Saturday, April 1, 2023

 

 ## Published in



[IEEE Journal of Solid-State Circuits ( Volume: 58, Issue: 4, April 2023)](https://ieeexplore.ieee.org/document/10011563)

 

 ## Research Area



[Circuits and VLSI Design](/research-area/circuits)

 

 

 ## Copyright



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