1. [Publications](/publications) 2. Large Language Model (LLM) for Standard Cell Layout Design Optimization # Large Language Model (LLM) for Standard Cell Layout Design Optimization ![](/sites/default/files/styles/wide/public/publications/CellClusterAgent.png?itok=Kjznu4Hl) Standard cells are essential components of modern digital circuit designs. With process technologies advancing toward 2nm, more routability issues have arisen due to the decreasing number of routing tracks, increasing number and complexity of design rules, and strict patterning rules. The state-of-the-art standard cell design automation framework is able to automatically design standard cell layouts in advanced nodes, but it is still struggling to generate highly competitive Performance-Power-Area (PPA) and routable cell layouts for complex sequential cell designs. Consequently, a novel and efficient methodology incorporating the expertise of experienced human designers to incrementally optimize the PPA of cell layouts is highly necessary and essential. High-quality device clustering, with consideration of netlist topology, diffusion sharing/break and routability in the layouts, can reduce complexity and assist in finding highly competitive PPA, and routable layouts faster. In this paper, we leverage the natural language and reasoning ability of Large Language Model (LLM) to generate high-quality cluster constraints incrementally to optimize the cell layout PPA and debug the routability with ReAct prompting. On a benchmark of sequential standard cells in 2nm, we demonstrate that the proposed method not only achieves up to 19.4% smaller cell area, but also generates 23.5% more LVS/DRC clean cell layouts than previous work. In summary, the proposed method not only successfully reduces cell area by 4.65% on average, but also is able to fix routability in the cell layout designs. ## Authors [Chia-Tung (Mark) Ho](/person/chia-tung-mark-ho) Mark Haoxing Ren (NVIDIA) ## Publication Date Friday, June 28, 2024 ## Published in [The First IEEE International Workshop on LLM-Aided Design (LAD'24)](https://arxiv.org/abs/2406.06549) ## Research Area [Artificial Intelligence and Machine Learning ](/research-area/machine-learning-artificial-intelligence) [Circuits and VLSI Design](/research-area/circuits) [Generative AI](/research-area/generative-ai) ## Uploaded Files [Paper PDF](https://d1qx31qr3h6wln.cloudfront.net/publications/3_Ho.pdf "Open file in new window")9.78 MB ## Award Best Paper Award ## Copyright This material is posted here with permission of the IEEE. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to .