Trey Greer

Trey Greer

Trey Greer joined NVIDIA's Circuits Research Group in April 2009. Prior to joining NVIDIA, he has worked on a variety of high-performance interconnect and graphics projects at Rambus, Velio Communications, PixelFusion, and Hewlett-Packard.

Research Interests:

High Performance and Low Power Phase-Locked Loops, On-Chip Networks, High Speed Chip Interconnect, Advanced Packaging, Design Tools for Full-Custom VLSI.

A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications
A 0.54pJ/b 20Gb/s Ground-Referenced Single-Ended Short-Haul Serial Link in 28nm CMOS for Advanced Packaging Applications
A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS