Design Automation Research Group

Design Automation Research Group

NVIDIA Design Automation Research Group

Welcome to the homepage of NVIDIA’s Design Automation Research group. We do research in novel design automation methods to improve chip design quality and design productivity. Our projects cover many chip design processes, from RTL design to verification, from digital design to analog design, and from logic synthesis and physical design to sign-off and design-for-manufacturing. Key research areas include:

  • GPU-accelerated EDA tools: GPU computing power increases at a much faster pace than CPU. There is a great opportunity to scale EDA tools’ performance on GPU.
  • AI for EDA: We explore AI methods such as Bayesian optimization, reinforcement learning, and generative AI to solve difficult EDA problems.
  • LLM for Chip Design: Large language model is changing the world. We train custom LLMs for chip design and develop systems that leverage LLMs to perform chip design tasks.

We collaborate with other NVIDIA research groups, internal HW design teams, as well as major university research groups and commercial companies. Graduate students interested in interning with us are welcome to reach out directly to team members for more details.

News

Oct 2024 - We are organizing ICCAD'24 contest on LLM-Assisted Hardware Code Generation (link)

Oct 2024 - We are organizing ICCAD'24 contest on Scalable Logic Gate Sizing Using ML Techniques and GPU Acceleration (link)

Sep 2024 - Our work “PyHDL-Eval: An LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs” (paper link) won the Best Artifact Award at MLCAD 2024

August 2024 - Website goes live!

June 2024 - Our work “Large Language Model (LLM) for Standard Cell Layout Design Optimization” (paper link) won the Best Paper Award at LAD 2024

March 2024 - We organized the ISPD'24 contest (link) on the topic of GPU/ML-Enhanced Large Scale Global Routing

March 2024 - Our work “Novel Transformer Model Based Clustering Method for Standard Cell Design Automation” (paper link) won the Best Paper Award at ISPD 2024

Members

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Haoxing (Mark) Ren

Team Leader

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Chenhui Deng

Graph Learning for EDA, LLM for Chip Design

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Chia-Tung (Mark) Ho

LLM Agent for Chip Design, Machine Learning for VLSI, DTCO, Standard Cell Layout Automation

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Danny Liu

Reinforcement Learning, Machine Learning for EDA, Generative AI

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Haoyu Yang

AI/LLM for EDA, GPU-accelerated EDA, AI for MultiPhysics Simulation, AI for Semiconductor Manufacturing

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Mingjie Liu

Circuits and VLSI Design, Artificial Intelligence and Machine Learning

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Rongjian Liang

Machine Learning for EDA, EDA for Machine Learning

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Wen-Hao Liu

Circuits and VLSI Design

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Yanqing Zhang

GPU Accelerated EDA, Machine Learning for EDA, GPU Accelerated Simulation

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Yi-Chen Lu

Physical Design, Machine Learning for EDA

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Yunsheng Bai

Formal Verification, Machine Learning for EDA

Publications

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Differentiable Edge-based OPC

2024 ACM/IEEE International Conference on Computer-Aided Design (ICCAD)

Large Language Model (LLM) for Standard Cell Layout Design Optimization

The First IEEE International Workshop on LLM-Aided Design (LAD)
Best Paper Award

Challenges for Automating PCB Layout (Invited)

2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)