A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS

This paper describes a 6.25-Gb/s 14-mW transceiver in 90-nm CMOS for chip-to-chip applications. The transceiver employs a number of features for reducing power consumption, including a shared LC-PLL clock multiplier, an inductor-loaded resonant clock distribution network, a low- and programmable-swing voltage-mode transmitter, software-controlled clock and data recovery (CDR) and adaptive equalization within the receiver, and a novel PLL-based phase rotator for the CDR. The design can operate with channel attenuation of -15 dB or greater at a bit-error rate of 10-15 or less, while consuming less than 2.25 mW/Gb/s per transceiver.

Authors: 
Robert Palmer (NVIDIA)
Andy Fuller (Duke University)
John Eyles (NVIDIA)
Mark Horowitz (Stanford)
Publication Date: 
Saturday, December 1, 2007
Research Area: