A 28nm 2Mbit 6T SRAM with Highly Configurable Write Assist Implementation and Capacitor Based Sense Amplifier Input Offset Compen

Authors: 
Mahmut Sinangil (NVIDIA)
Andy Gotterba (NVIDIA)
Jesse Wang (NVIDIA)
Jason Golbus (NVIDIA)
Publication Date: 
Monday, February 1, 2016
Research Area: