An Energy Efficient Time-sharing Pyramid Pipeline for Multi-resolution Computer Vision

We introduce an energy efficient time-sharing pyramid pipeline architecture designed for multi-resolution image analysis in mobile computer vision. The time-sharing pipeline efficiently reduces the off-chip memory traffic by re-organizing the data storage and processing order of an image pyramid. We build a parameterized image pyramid hardware generator and successfully evaluate the overall pyramid design space. Our results demonstrate that the time-sharing pyramid pipeline achieves about 50% of hardware savings in terms of area and power consumption compared to the traditional linear pipeline implementation. We also implement the multi-resolution Lucas-Kanade optical flow algorithm on the time-sharing pipeline, and demonstrate an order of magnitude savings in off-chip memory traffic and system energy consumption.

Authors: 
Qiuling Zhu (CMU)
Navjot Garg (NVIDIA)
Yun-Ta Tsai (NVIDIA)
Kari Pulli (NVIDIA)
Publication Date: 
Tuesday, October 1, 2013
Research Area: 
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