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Circuits and VLSI Design

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Circuits and VLSI Design

2020

FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning

Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Haoxing (Mark) Ren, Yanqing Zhang, Brucek Khailany, Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza

PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network

Zhiyao Xie, Haoxing (Mark) Ren, Brucek Khailany, Ye Sheng, Santosh Santosh, Jiang Hu, Yiran Chen

2019

MAGNet: A Modular Accelerator Generator for Neural Networks

Rangharajan Venkatesan, Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matt Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Yanqing Zhang, Brian Zimmer, William Dally, Joel Emer, Steve Keckler, Brucek Khailany

Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture

Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Brucek Khailany, Steve Keckler

Best Paper award
IEEE Micro Top Picks in Computer Architecture (Honorable Mention)

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator Designed with a High-Productivity VLSI Methodology

Rangharajan Venkatesan, Sophia Shao, Brian Zimmer, Jason Clemons, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Steve Keckler, Brucek Khailany

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm

Brian Zimmer, Rangharajan Venkatesan, Sophia Shao, Jason Clemons, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Steve Keckler, Brucek Khailany

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement

Yibo Lin, Shounak Dhar, Wuxi Li, Haoxing (Mark) Ren, Brucek Khailany, David Z. Pan

DAC 2019 Best Paper Award

High Performance Graph Convolutional Networks with Applications in Testability Analysis

Yuzhe Ma, Haoxing (Mark) Ren, Brucek Khailany, Harbinder Sikka, Lijuan Luo, Karthikeyan Natarajan, Bei Yu

PRIMAL: Power Inference using Machine Learning

Yuan Zhou, Haoxing (Mark) Ren, Yanqing Zhang, Ben Keller, Brucek Khailany, Zhiru Zhang

Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference

Angad S. Rekhi, Brian Zimmer, Nikola Nedovic, Nigxi Liu, Rangharajan Venkatesan, Miaorong Wang, Brucek Khailany, William Dally, Tom Gray

A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET

Matt Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Stephen Tell, Brian Zimmer, Tezaswi Raja, Kevin Zhou, William Dally, Brucek Khailany

ASYNC 2019 Best Paper Award

Voltage-Follower Coupling Quadrature Oscillator with Embedded Phase-Interpolator in 16nm FinFET

Xi Chen, Sanquan Song, John Poulton, Nikola Nedovic, Brian Zimmer, Stephen Tell, Tom Gray

Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model

Yu-Hung Huang, Zhiyao Xie, Guan-Qi Fang, Tao-Chun Yu, Haoxing (Mark) Ren, Shao-Yun Fang, Yiran Chen, Jiang Hu

A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator

John Poulton, John Wilson, Walker Turner, Brian Zimmer, Xi Chen, Sudhir Kudva, Sanquan Song, Stephen Tell, Nikola Nedovic, Wenxu Zhao, Sunil Sudhakaran, Tom Gray, William Dally

2018

RouteNet: Routability Prediction for Mixed-size Designs using Convolutional Neural Network

Zhiyao Xie, Yu-Hung Huang, Guan-Qi Fang, Haoxing (Mark) Ren, Shao-Yun Fang, Yiran Chen, Hu Jiang

A Modular Digital VLSI Flow for High-Productivity SoC Design

Brucek Khailany, Evgeni Krimer, Rangharajan Venkatesan, Jason Clemons, Joel Emer, Matt Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Pinckney, Sophia Shao, Shreesha Srinath, Christopher Torng, Sam (Likun) Xi, Yanqing Zhang, Brian Zimmer

Hardware-Enabled Artificial Intelligence

William Dally, Tom Gray, John Poulton, Brucek Khailany, John Wilson, Larry Dennison

Ground-Referenced Signaling for Intra-Chip and Short-Reach Chip-to-Chip Interconnects

Walker Turner, John Poulton, John Wilson, Xi Chen, Stephen Tell, Matt Fojtik, Trey Greer, Brian Zimmer, Sanquan Song, Nikola Nedovic, Sudhir Kudva, Sunil Sudhakaran, Rizwan Bashirullah, Wenxu Zhao, William Dally, Tom Gray

A Switching Linear Regulator Based on a Fast-Self-Clocked Comparator with Very Low Probability of Meta-stability and a Parallel Analog Ripple Control Module

Sudhir Kudva, Sanquan Song, John Poulton, John Wilson, Wenxu Zhao, Tom Gray

A 1.17pJ/b 25Gb/s/pin Ground-Referenced Single Ended Serial Link for Off- and On-Package Communication in 16nm CMOS Using a Process- and Temperature-Adaptive Voltage Regulator

John Wilson, Walker Turner, John Poulton, Brian Zimmer, Xi Chen, Sanquan Song, Stephen Tell, Nikola Nedovic, Wenxu Zhao, Sunil Sudhakaran, Tom Gray, William Dally

2017

Xylem: Enhancing Vertical Thermal Conduction in 3D Processor-Memory Stacks

Aditya Agrawal, Josep Torrellas, Sachin Idgunji

Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology

Vivek Seshadri, Donghyuk Lee, Thomas Mullins, Hasan Hassan, Amirali Boroumand, Jeremie Kim, Michael A. Kozuch, Onur Mutlu, Phillip B. Gibbons, Todd C. Mowry

Detecting and Mitigating Data-Dependent DRAM Failures by Exploiting Current Memory Content

Samira Khan, Chris Wilkerson, Zhe Wang, Alaa R. Alameldeen, Donghyuk Lee, Onur Mutlu

2016

Snatch: Opportunistically Reassigning Power Allocation between Processor and Memory in 3D Stacks

Dimitrios Skarlatos, Renji Thomas, Aditya Agrawal, Shibin Qin, Robert Pilawa-Podgurski, Ulya R. Karpuzcu, Radu Teodorescu, Nam Sung Kim, Josep Torrellas

Hybrid Modulation for Near Zero Display Latency

Trey Greer, Josef Spjut, David Luebke, Turner Whitted

Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks

Divya Akella Kamakshi, Matt Fojtik, Brucek Khailany, Sudhir Kudva, Yaping Zhou, Benton H. Calhoun

ASYNC 2016 Best Paper Award Nominee

Current parking regulator for zero droop/overshoot load transient response

Sudhir Kudva, William Dally, Trey Greer, Tom Gray

A 6.5-to-23.3fJ/b/mm Balanced Charge-Recycling Bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with Clock Forwarding and Low-Crosstalk Contraflow Wiring

John Wilson, Matt Fojtik, John Poulton, Xi Chen, Stephen Tell, Trey Greer, Tom Gray, William Dally

A 28nm 2Mbit 6T SRAM with Highly Configurable Write Assist Implementation and Capacitor Based Sense Amplifier Input Offset Compen

Mahmut Sinangil, John Poulton, Matt Fojtik, Trey Greer, Stephen Tell, Andy Gotterba, Jesse Wang, Jason Golbus, William Dally, Tom Gray