Publications

Our publications provide insight into some of our leading-edge research.

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2016

Counterexamples and Proof Loophole for the C/C++ to POWER and ARMv7 Trailing-Sync Compiler Mappings
Yatin A. Manerkar, Caroline Trippel, Daniel Lustig, Michael Pellauer, Margaret Martonosi
Snatch: Opportunistically Reassigning Power Allocation between Processor and Memory in 3D Stacks
Dimitrios Skarlatos, Renji Thomas, Aditya Agrawal, Shibin Qin, Robert Pilawa-Podgurski, Ulya R. Karpuzcu, Radu Teodorescu, Nam Sung Kim, Josep Torrellas
CANDY: Enabling Coherent DRAM Caches for Multi-Node Systems
Chiachen Chou, Aamer Jaleel, Moinuddin Qureshi
Co-Designing Accelerators and SoC Interfaces Using gem5-Aladdin
Yakun Sophia Zhao, Sam (Likun) Xi, Vijayalakshmi Srinivasan, Gu-Yeon Wei, David Brooks
Data-Centric Execution of Speculative Parallel Programs
Mark C. Jeffrey, Suvinay Subramanian, Maleen Abeydeera, Joel Emer, Daniel Sanchez
A Patch Memory System For Image Processing and Computer Vision.
Jason Clemons, Chih-Chi Cheng, Iuri Frosio, Daniel Johnson, Steve Keckler
vDNN: Virtualized Deep Neural Networks for Scalable, Memory-Efficient Neural Network Design.
Minsoo Rhu, Natalia Gimelshein, Jason Clemons, Arslan Zulfiqar, Steve Keckler
The Bunker Cache for Spatio-Value Approximation
Joshua San Miguel, Jorge Albericio, Aamer Jaleel, Natalie Enright Jerger
Approxilyzer: Towards A Systematic Framework for Instruction-Level Approximate Computing and its Application to Hardware Resiliency
Radha Venkatagiri, Abdulrahman Mahmoud, Siva Hari, Sarita Adve
CLARA: Circular Linked-List Auto- and Self-Refresh Architecture
Aditya Agrawal, Mike O'Connor, Evgeny Bolotin, Niladrish Chatterjee, Joel Emer, Steve Keckler
Automatically Exploiting Implicit Pipeline Parallelism from Multiple Dependent Kernels for GPUs
Gwangsun Kim, Jiyun Jeong, John Kim, Mark Stephenson
TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA
Caroline Trippel, Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi
EIE: Efficient Inference Engine on Compressed Deep Neural Network
Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark Horowitz, William Dally
Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks
Yu-Hsin Chen, Joel Emer, Vivienne Sze
Accelerating Dependent Cache Misses with an Enhanced Memory Controller
Milad Hashemi, Khubaib, Eiman Ebrahimi, Onur Mutlu, Yale N. Patt
Bit-Plane Compression: Transforming Data for Better Compression in Many-core Architectures
Jungrae Kim, Michael B. Sullivan, Esha Choukse, Mattan Erez
LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches
Hsiang-Yun Cheng, Jishen Zhao, Jack Sampson, Mary Jane Irwin, Aamer Jaleel, Yu Lu, Yuan Xie
Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems
Kevin Hsieh, Eiman Ebrahimi, Gwangsun Kim, Niladrish Chatterjee, Mike O'Connor, Nandita Vijaykumar, Onur Mutlu, Steve Keckler
All-Inclusive ECC: Thorough End-to-End Protection for Reliable Computer Memory
Jungrae Kim, Michael B. Sullivan, Sangkug Lym, Mattan Erez
A Real-time Energy-Efficient Superpixel Hardware Accelerator for Mobile Computer Vision Applications
Injoon Hong, Jason Clemons, Rangharajan Venkatesan, Iuri Frosio, Brucek Khailany, Steve Keckler
Selective GPU Caches to Eliminate CPU-GPU HW Cache Coherence
Neha Agarwal, David Nellans, Eiman Ebrahimi, Thomas F. Wenisch, John Danskin, Steve Keckler
Towards High Performance Paged Memory for GPUs
Tianhao Zheng, David Nellans, Arslan Zulfiqar, Mark Stephenson, Steve Keckler
A Case for Toggle-Aware Compression for GPU Systems
Gennady Pekhimenko, Evgeny Bolotin, Nandita Vijaykumar, Onur Mutlu, Todd C. Mowry, Steve Keckler
An Analytical Model for Hardened Latch Selection and Exploration
Michael B. Sullivan, Brian Zimmer, Siva Hari, Timothy Tsai, Steve Keckler
vDNN: Virtualized Deep Neural Networks for Scalable, Memory-Efficient Neural Network Design
Minsoo Rhu, Natalia Gimelshein, Jason Clemons, Arslan Zulfiqar, Steve Keckler

2015

CCICheck: Using μhb Graphs to Verify the Coherence-Consistency Interface
Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi
A Scalable Architecture for Ordered Parallelism
Mark C. Jeffery, Suvinay Subramanian, Cong Yang, Joel Emer, Daniel Sanchez
A Fast and Accurate Analytical Technique to Compute the AVF of Sequential Bits in a Processor
Steve Raasch, Arijis Biswas, Jon Stephan, Paul Racunas, Joel Emer
Exploiting Asymmetry in Booth-Encoded Multipliers for Reduced Energy Multiplication
Mike O'Connor, Earl Swartzlander, Jr.
Anatomy of GPU Memory System for Multi-Application Execution
Adwait Jog, Onur Kayiran, Tuba Kesten, Ashutosh Pattnaik, Evgeny Bolotin, Niladrish Chatterjee, Steve Keckler, Mahmut T. Kandemir, Chita R. Das
GPU Computing Pipeline Inefficiencies and Optimization Opportunities in Heterogeneous CPU-GPU Processors
Joel Hestness, Steve Keckler, David A. Wood
Scavenger: Automating the Construction of Application-Optimized Memory Hierarchies
Hsin-Jung Yang, Kermin Fleming, Michael Adler, Felix Winterstein, Joel Emer