Nir Arad

Nir Arad joined NVIDIA Research in February 2014 as senior research scientist in the Networking Research group. Prior to NVIDIA, he worked 6 years for Mellanox Technologies Limited, based at Yokneam, Israel, as a senior architect. Prior to Mellanox, Nir worked 10 years for Marvell Israel Limited, also based at Yokneam, Israel, which is part of the Marvell Technology Group, based at Santa Clara, CA. Nir served as co-chair of the Link Working Group (LWG) of the Infiniband Trade Association (IBTA) between 2008 and 2013. Nir holds B.Sc. and a Master's degree, both in Electrical Engineering, from the Technion, Israel Institute of Technology. In the course of his career, Nir was responsible for multiple innovations and award winning products in the companies he worked for. He has 14 patents in various stages of application. You can find his detailed profile here.

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Mark Stephenson

Mark Stephenson joined NVIDIA in February 2014.  He is primarily interested in program analysis and code generation.  Before joining NVIDIA, Mark spent time at IBM Research, and the Massachusetts Institute of Technology, where he earned his PhD in 2006.

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Yanqing Zhang

Yanqing joined nVidia Research in January of 2014. Prior to joining nVidia, he was a research assistant at the Robust Low Power VLSI reserach group at the University of Virginia (UVA),  where he received his PhD degree in 2013. While at UVA, his research focuses were on low power SoCs, sub-threshold digital circuit design, variation aware timing closure, and variation aware circuit design. Since joining nVidia, his research directions include variation aware circuit design and circuit design methodology.

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Alexander Reshetov

Alexander Reshetov received his Ph.D. degree from Keldysh Institute for Applied Mathematics (in Russia).

He joined Nvidia in January 2014. Prior to NVIDIA, he worked for 17 years in Intel Labs on 3D graphics algorithms and applications, and two years at the Super-Conducting Super-Collider Laboratory in Texas, where he was designing control system for the accelerator.

Iuri Frosio

Iuri Frosio got his PhD in biomedical engineering at the Politecnico of Milan in 2006. He was a research fellow at the Computer Science Department of the University of Milan from 2003 and an assistant professor in the same department from 2006 to 2013. In the same period, he worked as a consultant for various companies in Italy and in the US. He joined NVIDIA in 2014 as senior research scientist. His research interests include image processing, computer vision, parallel programming and reinforcement learning.

Niladrish Chatterjee

Niladrish Chatterjee is a Senior Research Scientist in the Architecture Research Group.  His research focuses on realizing energy-efficient, high-performance memory and processor architectures that will power future supercomputers and artificially intelligent machines.

He received a PhD in Computer Engineering from the University of Utah in 2013, and a B.E. in Computer Science from Jadavpur University in 2007.

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Oreste Villa

Oreste Villa joined NVIDIA in March 2013. He is a senior research scientist in the Architecture Research Group working on system level simulation, binary instrumentation and transparent Multi-GPU support. Previously he was a research scientist at Pacific Northwest National Lab where he worked on high performance computing distributed applications, distributed runtimes, GPU accelerated graph algorithms and performance models. He received his Ph.D. in Computer Science from Politecnico di Milano (Italy) in 2008.

Matt Fojtik

Matt Fojtik joined the Circuits Research group of NVIDIA in October 2013. Prior to NVIDIA, he worked on various adaptive clocking projects, two-phase latch based timing, and low power microprocessor design. He received his B.S., M.S. and Ph.D. degrees in Electrical Engineering from the University of Michigan in 2008, 2010, and 2013 respectively.

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