Oreste Villa

Oreste Villa joined NVIDIA in March 2013. He is a senior research scientist in the Architecture Research Group working on system level simulation, binary instrumentation and transparent Multi-GPU support. Previously he was a research scientist at Pacific Northwest National Lab where he worked on high performance computing distributed applications, distributed runtimes, GPU accelerated graph algorithms and performance models. He received his Ph.D. in Computer Science from Politecnico di Milano (Italy) in 2008.

Matt Fojtik

Matt Fojtik joined the Circuits Research group of NVIDIA in October 2013. Prior to NVIDIA, he worked on various adaptive clocking projects, two-phase latch based timing, and low power microprocessor design. He received his B.S., M.S. and Ph.D. degrees in Electrical Engineering from the University of Michigan in 2008, 2010, and 2013 respectively.

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Larry Dennison

Dr. Dennison joined NVIDIA in September of 2013 and leads the Network Research Group.  His current research interests include large networks of GPUs, switch micro-architectures, network-on-chip and photonic interconnects.  At, NVIDIA, he was the principal investigator for the DesignForward project which was responsible for several GPU shared-memory concepts such as NVSHMEM and NCCL.  His team proposed development of a GPU shared memory fabric and developed the first NVSwitch architecture.

Prior to NVIDIA, he worked on software systems such as high-performance distributed applications, database scaling for the cloud and software-defined networking. He also architected and led the development of the ASIC chipset for the Avici Terabit Router which utilized a 3-D toroidal network. At BBN, Dr. Dennison was the principal investigator for MicroPathfinder, a wearable computer that connected to other wearables over a very low power RF network. Dr. Dennison holds Ph.D., M.S., and B.S. degrees from the Massachusetts Institute of Technology.

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Siva Hari

Siva Hari is a Senior Research Scientist in the Computer Architecture Research Group at NVIDIA.  His current research focus is on making GPUs resilient through architecture and software level solutions. He obtained his Ph.D. and M.S. degrees from the Computer Science Department at University of Illinois at Urbana-Champaign and Bachelor's degree from the Computer Science and Engineering Department at IIT Madras.

He was selected to receive the 2014 David J. Kuck Outstanding Ph.D. Thesis Award by the Computer Science Department at University of Illinois at Urbana-Champaign. He also received the W.J. Poppelbaum Memorial Award by the CS Department at University of Illinois in 2012 for academic merit and creativity in computer architecture. One of the papers he co-authored was selected for the IEEE Micro's Top Picks 2013 and another was recognized as the Best Paper Award Runner-up at DSN 2018.

Link to my personal webpage.

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Jan Kautz

Jan leads the Learning & Perception Research team at NVIDIA, working predominantly on computer vision and machine learning problems — from low-level vision (denoising, super-resolution, computational photography), geometric vision (structure from motion, SLAM, optical flow) to high-level vision (detection, recognition, classification), as well as fundamental machine learning algorithms. Before joining NVIDIA in 2013, Jan was a tenured faculty member at University College London. He holds a BSc in Computer Science from University of Erlangen-Nürnberg (1999), an MMath from the University of Waterloo (1999), received his PhD from the Max-Planck-Institut für Informatik (2003), and worked as a post-doc at the Massachusetts Institute of Technology (2003-2006). Jan is particularly interested in computational photography and imaging, computer vision, and computational displays, on which he has published many articles at various conferences including ACM SIGGRAPH, Eurographics, CVPR, ECCV, CHI, and many more. A full publication list is available on his web-page.

Jan was program co-chair of the Eurographics Symposium on Rendering 2007, program chair of the IEEE Symposium on Interactive Ray-Tracing 2008, program co-chair for Pacific Graphics 2011, and program chair of CVMP 2012. He co-chaired Eurographics 2014 and is on the editorial board of IEEE Transactions on Visualization & Computer Graphics and The Visual Computer.

My team is hiring world-class research scientists and/or post-docs in computer vision and machine learning! 

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Albert Sidelnik

Albert Sidelnik joined NVIDIA Research in July 2013. He completed his Ph.D in Computer Science from the University of Illinois at Urbana-Champaign. His area of research is developing new programming models and compiler optimizations for massively parallel architectures. He has previously interned at NVIDIA Research, IBM TJ Watson, and Cray Inc. In 2010, he was a member of the team that won the HPC Challenge Class II Award for most productive system. He is also a three-time recipient of the NVIDIA Graduate Fellowship.

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Shalini De Mello

Shalini joined the Mobile Visual Computing group within Nvidia Research in April 2013. From March 2011-2013, she worked as a Senior Mobile Computer Vision Engineer at Nvidia, where she designed and productized computer vision and computational photography solutions for mobile platforms and GPUs.

Previously, she worked as an Imaging and Architecture Scientist at Texas Instruments (2008-2010) desiging algorithms for the image signal processing pipeline of mobile phones. She has interned at AT&T Laboratories on their IPTV project and at Advanced Digital Imaging Research, LLC where she designed algorithms for 3D human face recognition.

Shalini received her Masters and Doctoral degrees in Electrical and Computer Engineering from the University of Texas at Austin in 2004 and 2008, respectively. She received a Bachelor of Engineering degree in Electronics and Electrical Communication Engineering from Punjab Engineering College, India, in 2002. She is a recipient of the Summer Research Fellowship 2001 awarded by the Jawaharlal Nehru Center for Advanced Scientific Research, Bangalore, India.

For a complete list of publications visit Google Scholar.

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Sudhir Kudva

Sudhir S. Kudva received the Bachelor of Engineering degree (B.E.) in Electronics and  Communcation Engineering from National Institute of Technology Karnataka, Suratkal, in 2004  Master of Engineering degree (M.E.) in Microelectronics from Indian Institute of Science, Bangalore, in 2006 and PhD from University of Minnesota, Twin Cities, in 2013. From 2006 -2008 he worked as Design Engineer at the AMD India Engineering Centre, Bangalore designing ROMs in 65nm and 45nm SOI technology. In summer of 2011 and fall of 2012, he interned at Intel corporation.  He joined circuit research group of Nvidia research in April 2013. 

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