Chia-Tung Ho received the B.S. and M.S. degrees in electrical engineering and computer science from National Chiao Tung University, Hsinchu, Taiwan, in 2011 and 2013, respectively, and the Ph.D. degree in electrical and computer engineering from the University of California San Diego, USA, in 2022. Chia-Tung has several years of industrial EDA experience under his belt. Before coming to US, he worked for IDM and EDA companies in Taiwan, developing in-house design for manufacturing (DFM) flow at Macronix, and fastSPICE at Mentor Graphics and Synopsys. During his PhD study, he worked with the Design Technology Co-Optimization (DTCO) team in Synopsys as a technical intern from 2019 to 2021, also as an AI resident in X, the Google moonshot factory for 9 months. His research interests include LLM for circuit design, DTCO pathfinding , reinforcement learning for circuit design, machine learning for VLSI design, Power Delivery Network (PDN) optimization, and power grid simulation.
