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Matt Fojtik

Matt Fojtik joined the Circuits Research group of NVIDIA in October 2013. Prior to NVIDIA, he worked on various adaptive clocking projects, two-phase latch based timing, and low power microprocessor design. He received his B.S., M.S. and Ph.D. degrees in Electrical Engineering from the University of Michigan in 2008, 2010, and 2013 respectively.

Additional Research Areas: 
Circuits and VLSI Design

Publications

MAGNet: A Modular Accelerator Generator for Neural Networks
Simba: Scaling Deep-Learning Inference withMulti-Chip-Module-Based Architecture
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator Designed with a High-Productivity VLSI Methodology
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm
A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET
A Modular Digital VLSI Flow for High-Productivity SoC Design
Ground-Referenced Signaling for Intra-Chip and Short-Reach Chip-to-Chip Interconnects
Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks
A 6.5-to-23.3fJ/b/mm Balanced Charge-Recycling Bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with Clock Forwarding and Low-Crosstalk Contraflow Wiring
A 28nm 2Mbit 6T SRAM with Highly Configurable Write Assist Implementation and Capacitor Based Sense Amplifier Input Offset Compen
A Pausible Bisynchronous FIFO for GALS Systems
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