People

Brucek Khailany

Brucek Khailany joined NVIDIA in 2009 and currently leads the ASIC & VLSI Research group.  During his time at NVIDIA, he has contributed to projects within research and product groups on topics spanning computer architecture, unit micro-architecture, and ASIC and VLSI design techniques.  Previously, Dr. Khailany was a Co-Founder and Principal Architect at Stream Processors, Inc. (SPI) where he led research and development activities related to highly-parallel programmable processor architectures. At SPI, he helped lead the development of the industry's first commercially-available stream processor architecture targeting signal and image processing applications. From 1997-2003, at Stanford University, he led the silicon implementation of the Imagine stream processor, a research chip that introduced the concepts of stream processing and efficient partitioned register organizations. He received his Ph.D. and Masters in Electrical Engineering from Stanford University and received B.S.E. degrees in Electrical Engineering and Computer Engineering from the University of Michigan.

Research Area(s)
Computer Architecture
Artificial Intelligence and Machine Learning
Main Field of Interest
Circuits and VLSI Design
Google Scholar
https://scholar.google.com/citations?hl=en&user=c4-bwRcAAAAJ

Publications

2022

HEAT: Hardware-Efficient Automatic Tensor Decomposition for Transformer Compression
Jiaqi Gu, Ben Keller, Jean Kossaifi, Anima Anandkumar, Brucek Khailany, David Z. Pan
Workshop on ML for Systems at NeurIPS
Spotlight Paper
An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design
Mingjie Liu, Haoyu Yang, Zongyi Li, Kumara Sastry, Saumyadip Mukhopadhyay, Selim Dogru, Anima Anandkumar, David Z. Pan, Brucek Khailany, Mark Ren
Workshop on ML for Systems at NeurIPS
LNS-Madam: Low-Precision Training in Logarithmic Number System Using Multiplicative Weight Update
Jiawei Zhao, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, Mustafa Ali, Ming-Yu Liu, Brucek Khailany, William Dally, Anima Anandkumar
IEEE Transactions on Computers (Volume: 71, Issue: 12, 01 December 2022)
TransSizer: A Novel Transformer-Based Fast Gate Sizer
Siddhartha Nath, Geraldo Pradipta, Corey Hu, Tian Yang, Brucek Khailany, Mark Ren
2022 International Conference on Computer-Aided Design
XT-PRAGGMA: Crosstalk Pessimism Reduction Accessible by GPU Gate-level Simulations and Machine Learning
Vidya Chhabria, Ben Keller, Yanqing Zhang, Sandeep Vollala, Sreedhar Patty, Mark Ren, Brucek Khailany
MLCAD '22: Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD
From RTL to CUDA: A GPU Acceleration Flow for RTL Simulation with Batch Stimulus
Dian-Lun Lin, Mark Ren, Yanqing Zhang, Brucek Khailany, Tsung-Wei Huang
51st International Conference on Parallel Processing (ICPP '22)
Optimal Clipping and Magnitude-aware Differentiation for Improved Quantization-aware Training
Charbel Sakr, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, Brucek Khailany, William Dally
2022 International Conference on Machine Learning (ICML)
A 17–95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm
Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen Tell, Brian Zimmer, William Dally, Tom Gray, Brucek Khailany
2022 Symposium on VLSI Technology & Circuits Digest of Technical Papers
AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies
Hao Chen, Walker Turner, Sanquan Song, Keren Zhu, George Kokai, Brian Zimmer, Tom Gray, Brucek Khailany, Mark Ren
International Symposium on Physical Design 2022
Generic Lithography Modeling with Dual-band Optics-Inspired Neural Networks
Haoyu Yang, Zongyi Li, Kumara Sastry, Saumyadip Mukhopadhyay, Mark Kilgard, Anima Anandkumar, Brucek Khailany, Vivek Singh, Mark Ren
2022 Design Automation Conference
GATSPI: GPU Accelerated Gate-Level Simulation for Power Improvement
Yanqing Zhang, Mark Ren, Akshay Sridharan, Brucek Khailany
2022 Design Automation Conference
Machine Learning and Algorithms: Let Us Team Up for EDA
Mark Ren, Brucek Khailany, Matt Fojtik, Yanqing Zhang
IEEE Design & Test

2021

NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning
Mark Ren, Matt Fojtik, Brucek Khailany
Design Automation Conference (DAC) 2021 (Invited special session paper)
Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers
Jacob R. Stevens, Rangharajan Venkatesan, Steve Dai, Brucek Khailany, Anand Raghunathan
Design Automation Conference (DAC) 2021
IPA: Floorplan-Aware SystemC Interconnect Performance Modeling and Generation for HLS-based SoCs
Nathaniel Pinckney, Rangharajan Venkatesan, Ben Keller, Brucek Khailany
IEEE/ACM International Conference on Computer-Aided Design (ICCAD ’21)
Simba: scaling deep-learning inference with chiplet-based architecture
Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Brucek Khailany, Steve Keckler
Communications of the ACM
ACM Research Highlight
VS-QUANT: Per-Vector Scaled Quantization for Accurate Low-Precision Neural Network Inference
Steve Dai, Rangharajan Venkatesan, Mark Ren, Brian Zimmer, William Dally, Brucek Khailany
MLSys 2021
Verifying High-Level Latency-Insensitive Designs with Formal Model Checking
Steve Dai, Alicia Klinefelter, Mark Ren, Rangharajan Venkatesan, Ben Keller, Nathaniel Pinckney, Brucek Khailany
arXiv
MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification
Vidya A. Chhabria, Yanqing Zhang, Mark Ren, Ben Keller, Brucek Khailany, Sachin S. Sapatnekar
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization
Mingjie Liu, Walker Turner, George Kokai, David Z. Pan, Brucek Khailany, Mark Ren
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)

2020

NVCell: Generate Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning
Mark Ren, Matt Fojtik, Brucek Khailany
Workshop on ML for Systems at NeurIPS
Opportunities for RTL and Gate Level Simulation using GPUs
Yanqing Zhang, Mark Ren, Brucek Khailany
IEEE/ACM International Conference on Computer-Aided Design (ICCAD ’20)
Accelerating Chip Design with Machine Learning
Brucek Khailany, Mark Ren, Steve Dai, Saad Godil, Ben Keller, Robert Kirby, Alicia Klinefelter, Rangharajan Venkatesan, Yanqing Zhang, Bryan Catanzaro, William Dally
IEEE Micro
GRANNITE: Graph Neural Network Inference for Transferable Power Estimation
Yanqing Zhang, Mark Ren, Brucek Khailany
Design Automation Conference (DAC) 2020
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement
Yibo Lin, Zixuan Jiang, Jiaqi Gu, Wuxi Li, Shounak Dhar, Mark Ren, Brucek Khailany, David Z. Pan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (…
2021 IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award
ABCDPlace: Accelerated Batch-based Concurrent Detailed Placement on Multi-threaded CPUs and GPUs
Yibo Lin, Wuxi Li, Jiaqi Gu, Mark Ren, Brucek Khailany, David Z. Pan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (…
A 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm
Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Steve Keckler, Brucek Khailany
IEEE Journal of Solid-State Circuits (JSSC)
JSSC 2020 Best Paper Award
FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning
Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Mark Ren, Yanqing Zhang, Brucek Khailany, Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza
ASP-DAC 2020
PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network
Zhiyao Xie, Mark Ren, Brucek Khailany, Ye Sheng, Santosh Santosh, Jiang Hu, Yiran Chen
ASP-DAC 2020

2019

MAGNet: A Modular Accelerator Generator for Neural Networks
Rangharajan Venkatesan, Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matt Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Yanqing Zhang, Brian Zimmer, William Dally, Joel Emer, Steve Keckler, Brucek Khailany
International Conference On Computer Aided Design (ICCAD)
Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture
Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Brucek Khailany, Steve Keckler
International Symposium on Microarchitecture (MICRO)
MICRO 52 Best Paper Award
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator Designed with a High-Productivity VLSI Methodology
Rangharajan Venkatesan, Sophia Shao, Brian Zimmer, Jason Clemons, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Steve Keckler, Brucek Khailany
Hot Chips: A Symposium on High Performance Chips
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm
Brian Zimmer, Rangharajan Venkatesan, Sophia Shao, Jason Clemons, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Steve Keckler, Brucek Khailany
Symposium on VLSI Circuits
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement
Yibo Lin, Shounak Dhar, Wuxi Li, Mark Ren, Brucek Khailany, David Z. Pan
Design Automation Conference (DAC) 2019
DAC 2019 Best Paper Award
PRIMAL: Power Inference using Machine Learning
Yuan Zhou, Mark Ren, Yanqing Zhang, Ben Keller, Brucek Khailany, Zhiru Zhang
Design Automation Conference (DAC)
High Performance Graph Convolutional Networks with Applications in Testability Analysis
Yuzhe Ma, Mark Ren, Brucek Khailany, Harbinder Sikka, Lijuan Luo, Karthikeyan Natarajan, Bei Yu
Design Automation Conference (DAC)
Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference
Angad S. Rekhi, Brian Zimmer, Nikola Nedovic, Nigxi Liu, Rangharajan Venkatesan, Miaorong Wang, Brucek Khailany, William Dally, Tom Gray
Design Automation Conference (DAC)
A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET
Matt Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Stephen Tell, Brian Zimmer, Tezaswi Raja, Kevin Zhou, William Dally, Brucek Khailany
ASYNC 2019
ASYNC 2019 Best Paper Award
Timeloop: A Systematic Approach to DNN Accelerator Evaluation
Angshuman Parashar, Priyanka Raina, Yakun Sophia Shao, Yu-Hsin Chen, Victor A. Ying, Anurag Mukkara, Rangharajan Venkatesan, Brucek Khailany, Steve Keckler, Joel Emer
International Symposium on Performance Analysis of Systems and Software (ISPASS)

2018

A Modular Digital VLSI Flow for High-Productivity SoC Design
Brucek Khailany, Evgeni Krimer, Rangharajan Venkatesan, Jason Clemons, Joel Emer, Matt Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Pinckney, Sophia Shao, Shreesha Srinath, Christopher Torng, Sam (Likun) Xi, Yanqing Zhang, Brian Zimmer
Design Automation Conference (DAC)
Hardware-Enabled Artificial Intelligence
William Dally, Tom Gray, John Poulton, Brucek Khailany, John Wilson, Larry Dennison
Symposia on VLSI Technology and Circuits

2017

SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks
Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel Emer, Steve Keckler, William Dally
International Symposium on Computer Architecture (ISCA)

2016

A Real-time Energy-Efficient Superpixel Hardware Accelerator for Mobile Computer Vision Applications
Injoon Hong, Jason Clemons, Rangharajan Venkatesan, Iuri Frosio, Brucek Khailany, Steve Keckler
Design Automation Conference (DAC)
Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks
Divya Akella Kamakshi, Matt Fojtik, Brucek Khailany, Sudhir Kudva, Yaping Zhou, Benton H. Calhoun
ASYNC 2016
ASYNC 2016 Best Paper Award Nominee

2015

A Pausible Bisynchronous FIFO for GALS Systems
Ben Keller, Matt Fojtik, Brucek Khailany
ASYNC 2015

2012

Unifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor
Mark Gebhart, Steve Keckler, Brucek Khailany, Ronny Krashinsky, William Dally
International Symposium on Microarchitecture (MICRO)

2011

CudaDMA: Optimizing GPU Memory Bandwidth via Warp Specialization
Michael Bauer, Henry Cook, Brucek Khailany
SC '11
GPUs and the Future of Parallel Computing
Steve Keckler, William Dally, Brucek Khailany, Michael Garland, David Glasco
IEEE Micro