Scaling the Power Wall: A Path to Exascale

Modern scientific discovery is driven by an insatiable demand for computing performance. The HPC community is targeting development of supercomputers able to sustain 1 ExaFlops by the year 2020 and power consumption is the primary obstacle to achieving this goal. A combination of architectural improvements, circuit design, and manufacturing technologies must provide over a 20× improvement in energy efficiency. In this paper, we present some of the progress NVIDIA is making toward the design of Exascale systems by tailoring features to address the scaling challenges of performance and energy efficiency. We evaluate several architectural concepts for a set of HPC applications demonstrating expected energy efficiency improvements resulting from circuit and packaging innovations such as low-voltage SRAM, low-energy signaling, and on-package memory. Finally, we discuss the scaling of these features with respect to future process technologies and provide power and performance projections for our Exascale research architecture.


Daniel Johnson (NVIDIA)
Evgeny Bolotin (NVIDIA)
Justin Luitjens (NVIDIA)
Nikolai Sakharnykh (NVIDIA)
Peng Wang (NVIDIA)
Paulius Micikevicius (NVIDIA)
Anthony Scudiero (NVIDIA)

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