Research Areas

Computer Architecture

Associated Publications

2023

VaPr: Variable-Precision Tensors to Accelerate Robot Motion Planning
Yu-Shun Hsiao, Siva Hari, Balakumar Sundaralingam, Jason Yik, Thierry Tambe, Charbel Sakr, Steve Keckler, Vijay Janapa Reddi
IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS 2023)
cuCatch: A Debugging Tool for Efficiently Catching Memory Safety Violations in CUDA Applications
Mohamed Tarek Ibn Ziad, Sana Damani, Aamer Jaleel, Stephen W. Keckler, Mark Stephenson
ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI)
Implicit Memory Tagging: No-Overhead Memory Safety Using Alias-Free Tagged ECC
Michael B. Sullivan, Mohamed Tarek Ibn Ziad, Aamer Jaleel, Stephen W. Keckler
International Symposium on Computer Architecture (ISCA)
CuRobo: Parallelized Collision-Free Robot Motion Generation
Balakumar Sundaralingam, Siva Hari, Adam Fishman, Caelan Garrett, Karl Van Wyk, Valts Blukis, Alexander Millane, Helen Oleynikova, Ankur Handa, Fabio Ramos, Nathan Ratliff, Dieter Fox
IEEE International Conference on Robotics and Automation (ICRA)
A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm
Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen Tell, Brian Zimmer, Charbel Sakr, William Dally, Tom Gray, Brucek Khailany
Journal of Solid-State Circuits

2022

HEAT: Hardware-Efficient Automatic Tensor Decomposition for Transformer Compression
Jiaqi Gu, Ben Keller, Jean Kossaifi, Anima Anandkumar, Brucek Khailany, David Z. Pan
Workshop on ML for Systems at NeurIPS
Spotlight Paper
LNS-Madam: Low-Precision Training in Logarithmic Number System Using Multiplicative Weight Update
Jiawei Zhao, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, Mustafa Ali, Ming-Yu Liu, Brucek Khailany, William Dally, Anima Anandkumar
IEEE Transactions on Computers (Volume: 71, Issue: 12, 01 December 2022)
Towards Precision-Aware Fault Tolerance Approaches for Mixed-Precision Applications
Bo Fang, Siva Hari, Timothy Tsai, Xinyi Li, Ganesh Gopalakrishnan, Ignacio Laguna, Kevin Barker, Ang Li
Workshop on Fault-Tolerance for HPC at Extreme Scale (FTXS)
Demystifying Map Space Exploration for NPUs
Sheng-Chun Kao, Angshuman Parashar, Po-An Tsai, Tushar Krishna
International Symposium on Workload Characterization (IISWC)
The Implications of Page Size Management on Graph Analytics
Aninda Manocha, Zi Yan, Esin Tureci, Juan Luis Aragón, David Nellans, Margaret Martonosi
International Symposium on Workload Characterization (IISWC)
Sparseloop: An Analytical Approach to Sparse Tensor Accelerator Modeling
Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel Emer
International Symposium on Microarchitecture (MICRO)
Distinguished Artifact award
SEC-BADAEC: An Efficient ECC With No Vacancy for Strong Memory Protection
Yuseok Song, Sangjae Park, Michael B. Sullivan, Jungrae Kim
IEEE Access
Self Adaptive Reconfigurable Arrays (SARA): Learning Flexible GEMM Accelerator Configuration and Mapping-space using ML
Ananda Samajdar, Eric Qin, Michael Pellauer, Tushar Krishna
Design Automation Conference (DAC)
Zhuyi: Perception Processing Rate Estimation for Safety in Autonomous Vehicles
Yu-Shun Hsiao, Siva Hari, Michał Filipiuk, Timothy Tsai, Michael B. Sullivan, Vijay Janapa Reddi, Vasu Singh, Steve Keckler
Design Automation Conference (DAC)
Ruby: Improving Hardware Efficiency for Tensor Algebra Accelerators Through Imperfect Factorization
Mark Horeni, Pooria Taheri, Po-An Tsai, Angshuman Parashar, Joel Emer, Siddharth Joshi
International Symposium on Performance Analysis of Systems and Software (ISPASS)
Exploiting Temporal Data Diversity for Detecting Safety-critical Faults in AV Compute Systems
Saurabh Jha, Shengkun Cui, Timothy Tsai, Siva Hari, Michael B. Sullivan, Zbigniew T. Kalbarczyk, Steve Keckler, Ravishankar K. Iyer
International Conference on Dependable Systems and Networks (DSN)
Mixed-Proxy Extensions for the NVIDIA PTX Memory Consistency Model
Daniel Lustig, Simon Cooksey, Olivier Giroux
International Symposium on Computer Architecture (ISCA), Industry Track
IEEE Micro Top Picks in Computer Architecture (Honorable Mention)
SIMD^2: A Generalized Matrix Instruction Set for Accelerating Tensor Computation beyond GEMM
Yunan Zhang, Po-An Tsai, Hung-Wei Tseng
International Symposium on Computer Architecture (ISCA)
A Formalism of DNN Accelerator Flexibility
Sheng-Chun Kao, Hyoukjun Kwon, Michael Pellauer, Angshuman Parashar, Tushar Krishna
SIGMETRICS
Learning A Continuous and Reconstructible Latent Space for Hardware Accelerator Design
Qijing Jenny Huang, Charles Hong, John Wawrzynek, Mahesh Subedar, Yakun Sophia Shao
International Symposium on Performance Analysis of Systems and Software (ISPASS)
Zhuyi: Perception Processing Rate Estimation for Safety in Autonomous Vehicles
Yu-Shun Hsiao, Siva Hari, Michał Filipiuk, Timothy Tsai, Michael B. Sullivan, Vijay Janapa Reddi, Vasu Singh, Steve Keckler
arXiv
Saving PAM4 Bus Energy with SMOREs: Sparse Multi-level Opportunistic Restricted Encodings
Mike O'Connor, Donghyuk Lee, Niladrish Chatterjee, Michael B. Sullivan, Steve Keckler
International Symposium on High-Performance Computer Architecture (HPCA)
Improving Locality of Irregular Updates with Hardware Assisted Propagation Blocking
Vignesh Balaji, Brandon Lucia
International Symposium on High Performance Computer Architecture (HPCA)
Best Paper nominee
Characterizing and Mitigating Soft Errors in GPU DRAM
Michael B. Sullivan, Nirmal R. Saxena, Mike O'Connor, Donghyuk Lee, Paul Racunas, Saurabh Hukerikar, Timothy Tsai, Siva Kumar Sastry Hari, Stephen W. Keckler
IEEE Micro (Issue: Top Picks of the 2021 Computer Architecture Conferences)
DiGamma: Domain-aware Genetic Algorithm for HW-Mapping Co-optimization for DNN Accelerators
Sheng-Chun Kao, Michael Pellauer, Angshuman Parashar, Tushar Krishna
Design, Automation & Test in Europe (DATE)
Marvel: A Data-Centric Approach for Mapping Deep Learning Operators on Spatial Accelerators
Prasanth Chatarasi, Hyoukjun Kwon, Angshuman Parashar, Michael Pellauer, Tushar Krishna, Vivek Sarkar
Transactions on Architecture and Code Optimization (TACO)
DAGguise: Mitigating Memory Timing Side Channels
Peter W. Deutsch, Yuheng Yang, Thomas Bourgeat, Jules Drean, Joel Emer, Mengjia Yan
International Conference on Architectural Support for Programming Languages and…
GPU Subwarp Interleaving
Sana Damani, Mark Stephenson, Ram Rangan, Daniel Johnson, Rishkul Kulkarni, Steve Keckler
International Symposium on High-Performance Computer Architecture (HPCA)
Accelerators
Steve Keckler, Dejan Milojicic
IEEE Computer

2021

GPU Domain Specialization via Composable On-Package Architecture
Yaosheng Fu, Evgeny Bolotin, Niladrish Chatterjee, David Nellans, Steve Keckler
ACM Transactions on Architecture and Code Optimization (TACO)
Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers
Jacob R. Stevens, Rangharajan Venkatesan, Steve Dai, Brucek Khailany, Anand Raghunathan
Design Automation Conference (DAC) 2021
Evolution of the Graphics Processing Unit (GPU)
William Dally, Steve Keckler, David B. Kirk
IEEE Micro Special Issue of the 50th Anniversary of the Microprocessor
Optimizing Selective Protection for CNN Resilience
Abdulrahman Mahmoud, Siva Hari, Christopher W. Fletcher, Sarita V. Adve, Charbel Sakr, Naresh Shanbhag, Pavlo Molchanov, Michael B. Sullivan, Timothy Tsai, Steve Keckler
International Symposium on Software Reliability Engineering (ISSRE)
Suraksha: A Framework to Analyze the Safety Implications of Perception Design Choices in AVs
Hengyu Zhao, Siva Hari, Timothy Tsai, Michael B. Sullivan, Steve Keckler, Jishen Zhao
International Symposium on Software Reliability Engineering (ISSRE)
GPS: A Global Publish-Subscribe Model for Multi-GPU Memory Management
Harini Muthukrishnan, Daniel Lustig, David Nellans, Thomas Wenisch
International Symposium on Microarchitecture (MICRO)
Best Paper nominee, IEEE Micro Top Picks in Computer Architecture (Honorable Mention)
Characterizing and Mitigating Soft Errors in GPU DRAM
Michael B. Sullivan, Nirmal Saxena, Mike O'Connor, Donghyuk Lee, Paul Racunas, Saurabh Hukerikar, Timothy Tsai, Siva Hari, Steve Keckler
International Symposium on Microarchitecture (MICRO)
IEEE Micro Top Picks in Computer Architecture
Union: A Unified HW-SW Co-Design Ecosystem in MLIR for Evaluating Tensor Operations on Spatial Accelerators
Geonhwa Jeong, Gokcen Kestor, Prasanth Chatarasi, Angshuman Parashar, Po-An Tsai, Sivasankaran Rajamanickam, Roberto Gioiosa, Tushar Krishna
Parallel Architectures and Compilation Techniques (PACT)
EMOGI: Efficient Memory-access for Out-of-memory Graph-traversal in GPUs
Seung Won Min, Vikram Sharma Mailthody, Zaid Qureshi, Jinjun Xiong, Eiman Ebrahimi, Wen-mei Hwu
Proceedings of the VLDB Endownment (VLDB)
Large Graph Convolutional Network Training with GPU-Oriented Data Communication Architecture
Seung Won Min, Kun Wu, Sitao Huang, Mert Hidayetoglu, Jinjun Xiong, Eiman Ebrahimi, Deming Chen, Wen-mei Hwu
Proceedings of the VLDB Endowment (VLDB)
NVBitFI: Dynamic Fault Injection for GPUs
Timothy Tsai, Siva Hari, Michael B. Sullivan, Oreste Villa, Steve Keckler
International Conference on Dependable Systems and Networks (DSN)
SpZip: Architectural Support for Effective Data Compression in Irregular Applications
Yifan Yang, Joel Emer, Daniel Sanchez
International Symposium on Computer Architecture (ISCA)
Efficient Multi-GPU Shared Memory via Automatic Optimization of Fine-Grained Transfers
Harini Muthukrishnan, David Nellans, Daniel Lustig, Jeffrey Fessler, Thomas Wenisch
International Symposium on Computer Architecture (ISCA)
Simba: scaling deep-learning inference with chiplet-based architecture
Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Brucek Khailany, Steve Keckler
Communications of the ACM
ACM Research Highlight
Demystifying GPU Reliability: Comparing and Combining Beam Experiments, Fault Simulation, and Profiling
Fernando Fernandes dos Santos, Siva Hari, Pedro Martins Basso, Luigi Carro, Paolo Rech
IEEE International Parallel & Distributed Processing Symposium (IPDPS)
Sparseloop: An Analytical, Energy-Focused Design Space Exploration Methodology for Sparse Tensor Accelerators
Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel Emer
International Symposium on Performance Analysis of Systems and Software (ISPASS)
GAMMA: Exploiting Gustavson’s Algorithm to Accelerate Sparse Matrix Multiplication
Guowei Zhang, Nithya Attaluri, Joel Emer, Daniel Sanchez
International Conference on Architectural Support for Programming Languages and…
Mind Mappings: Enabling Efficient Algorithm-Accelerator Mapping Space Search
Kartik Hegde, Po-An Tsai, Sitao Huang, Vikas Chandra, Angshuman Parashar, Christopher W. Fletcher
International Conference on Architectural Support for Programming Languages and…
VS-QUANT: Per-Vector Scaled Quantization for Accurate Low-Precision Neural Network Inference
Steve Dai, Rangharajan Venkatesan, Mark Ren, Brian Zimmer, William Dally, Brucek Khailany
MLSys 2021
GPU Domain Specialization via Composable On-Package Architecture
Yaosheng Fu, Evgeny Bolotin, Niladrish Chatterjee, David Nellans, Steve Keckler
arXiv
Learning Sparse Matrix Row Permutations for Efficient SpMM on GPU Architectures
Atefeh Mehrabi, Donghyuk Lee, Niladrish Chatterjee, Danial J. Sorin, Benjamin C. Lee, Mike O'Connor
International Symposium on Performance Analysis of Systems and Software (ISPASS)
Large Graph Convolutional Network Training with GPU-Oriented Data Communication Architecture
Seung Won Min, Kun Wu, Sitao Huang, Mert Hidayetoglu, Jinjun Xiong, Eiman Ebrahimi, Deming Chen, Wen-mei Hwu
ArXiv
PGZ: Automatic Zero-Value Code Specialization
Mark Stephenson, Ram Rangan
International Conference on Compiler Construction (CC)
Making Convolutions Resilient via Algorithm-Based Error Detection Techniques
Siva Hari, Michael B. Sullivan, Timothy Tsai, Steve Keckler
IEEE Transactions on Dependable and Secure Computing (TDSC)
Reduced Precision DWC: An Efficient Hardening Strategy for Mixed-Precision Architectures
Fernando F. dos Santos, Marcelo Brandalero, Michael B. Sullivan, Pedro M. Basso, Michael Hubner, Luigi Carro, Paolo Rech
IEEE Transactions on Computers
Heterogeneous Dataflow Accelerators for Multi-DNN Workloads
Hyoukjun Kwon, Liangzhen Lai, Michael Pellauer, Tushar Krishna, Yu-Hsin Chen, Vikas Chandra
International Symposium on High-Performance Computer Architecture (HPCA)
P-OPT: Practical Optimal Cache Replacement for Graph Analytics
Vignesh Balaji, Neal Crago, Aamer Jaleel, Brandon Lucia
International Symposium on High Performance Computer Architecture (HPCA)
Best Paper nominee
Need for Speed: Experiences Building a Trustworthy System-Level GPU Simulator.
Oreste Villa, Daniel Lustig, Zi Yan, Evgeny Bolotin, Yaosheng Fu, Niladrish Chatterjee, Ted Jiang, David Nellans
International Symposium on High Performance Computer Architecture (HPCA)
SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference
Jie-Fang Zhang, Ching-En Lee, Chester Liu, Yakun Sophia Shao, Steve Keckler, Zhengya Zhang
IEEE Journal of Solid-State Circuits (JSSC)
Hardware Abstractions for Targeting EDDO Architectures with the Polyhedral Model
Angshuman Parashar, Prasanth Chatarasi, Po-An Tsai
International Workshop on Polyhedral Compilation Techniques (IMPACT)
Flexion: A Quantitative Metric for Flexibility in DNN Accelerators
Hyoukjun Kwon, Michael Pellauer, Angshuman Parashar, Tushar Krishna
IEEE Computer Architecture Letters (CAL)

2020

The Architectural Implications of Distributed Reinforcement Learning on CPU-GPU Systems
Ahmet Inci, Evgeny Bolotin, Yaosheng Fu, Gal Dalal, Shie Mannor, David Nellans, Diana Marculescu
Workshop on Energy Efficient Machine Learning and Cognitive Computing (EMC2)
GPU-Trident: Efficient Modeling of Error Propagation in GPU Programs
Abdul Rehman Anwer, Guanpeng Li, Karthik Pattabiraman, Michael B. Sullivan, Timothy Tsai, Siva Hari
The International Conference for High Performance Computing, Networking, Storag…
Locality-Centric Data and Threadblock Management for Massive GPUs
Mahmoud Khairy, Vadim Nikiforov, David Nellans, Timothy G. Rogers
International Symposium on Microarchitecture (MICRO)
CaSA: End-to-end Quantitative Security Analysis of Randomly Mapped Caches
Thomas Bourgeat, Jules Drean, Yuheng Yang, Lillian Tsai, Joel Emer, Mengjia Yan
International Symposium on Microarchitecture (MICRO)
HarDNN: Fine-Grained Vulnerability Evaluation and Protection for Convolutional Neural Networks
Abdulrahman Mahmoud, Siva Hari, Christopher W. Fletcher, Sarita V. Adve, Charbel Sakr, Naresh Shanbhag, Pavlo Molchanov, Michael B. Sullivan, Timothy Tsai, Steve Keckler
SRC TECHCON
How to Evaluate Deep Neural Network Processors: TOPS/W (Alone) Considered Harmful
Vivienne Sze, Yu-Hsin Chen, Tien-Ju Yang, Joel Emer
IEEE Solid-State Circuits Magazine
Planaria: Dynamic Architecture Fission for Spatial Multi-Tenant Acceleration of Deep Neural Networks
Soroush Ghodrati, Byung Hoon Ahn, Joon Kyung Kim, Sean Kinzer, Brahmendra Reddy Yatham, Navateja Alla, Hardik Sharma, Mohammad Alian, Eiman Ebrahimi, Nam Sung Kim, Cliff Young, Hadi Esmaeilzadeh
International Symposium on Microarchitecture (MICRO)
PyTorchFI: A Runtime Perturbation Tool for DNNs
Abdulrahman Mahmoud, Neeraj Aggarwal, Alex Nobbe, Jose Rodrigo Sanchez Vicarte, Sarita V. Adve, Christopher W. Fletcher, Iuri Frosio, Siva Hari
Workshop on Dependable and Secure Machine Learning
EMOGI: Efficient Memory-access for Out-of-memory Graph-traversal In GPUs
Seung Won Min, Vikram Sharma Mailthody, Zaid Qureshi, Jinjun Xiong, Eiman Ebrahimi, Wen-mei Hwu
arXiv
Making Convolutions Resilient via Algorithm-Based Error Detection Techniques
Siva Hari, Michael B. Sullivan, Timothy Tsai, Steve Keckler
arXiv
There’s Plenty of Room at the Top: What Will Drive Computer Performance after Moore’s Law?
Charles E. Leiserson, Neil C. Thompson, Joel Emer, Bradley C. Kuszmaul, Butler W. Lampson, Daniel Sanchez , Tao B. Schardl
Science
Buddy Compression: Enabling Larger Memory for Deep Learning and HPC Workloads on GPUs
Esha Chouske, Michael B. Sullivan, Mike O'Connor, Mattan Erez, Jeff Pool, David Nellans, Steve Keckler
International Symposium on Computer Architecture (ISCA)
An In-Network Architecture for Accelerating Shared-Memory Multiprocessor Collectives
Benjamin Klenk, Ted Jiang, Greg Thorson, Larry Dennison
International Symposium on Computer Architecture (ISCA)
Estimating Silent Data Corruption Rates Using a Two-Level Model
Siva Hari, Paolo Rech, Timothy Tsai, Mark Stephenson, Arslan Zulfiqar, Michael B. Sullivan, Philip Shirvani, Paul Racunas, Joel Emer, Steve Keckler
arXiv
MAESTRO: A Data-Centric Approach to Understand Reuse, Performance, and Hardware Cost of DNN Mappings
Hyoukjun Kwon, Prasanth Chatarasi, Vivek Sarkar, Tushar Krishna, Michael Pellauer, Angshuman Parashar
IEEE Micro (Issue: Top Picks of the 2019 Computer Architecture Conferences)
BYOC: A "Bring Your Own Core" Framework for Heterogeneous-ISA Research
Jonathan Balkind, Katie Lim, Michael Schaffner, Fei Gao, Grigory Chirkov, Ang Li, Alexey Lavrov, Tri M. Nguyen, Yaosheng Fu, Florian Zaruba, Kunal Gulati, Luca Benini, David Wentzlaf
International Conference on Architectural Support for Programming Languages and…
Safecracker: Leaking Secrets through Compressed Caches
Po-An Tsai, Andres Sanchez, Christopher W. Fletcher, Daniel Sanchez
International Conference on Architectural Support for Programming Languages and…
IEEE Micro Top Picks in Computer Architecture
RealityCheck: Bringing Modularity, Hierarchy, and Abstraction to Automated Microarchitectural Memory Consistency Verification
Yatin A. Manerkar, Daniel Lustig, Margaret Martonosi
arXiv
Feature Map Vulnerability Evaluation in CNNs
Abdulrahman Mahmoud, Siva Hari, Christopher W. Fletcher, Sarita V. Adve, Charbel Sakr, Naresh Shanbhag, Pavlo Molchanov, Michael B. Sullivan, Timothy Tsai, Steve Keckler
Workshop on Secure and Resilient Autonomy
HarDNN: Feature Map Vulnerability Evaluation in CNNs
Abdulrahman Mahmoud, Siva Hari, Christopher W. Fletcher, Sarita V. Adve, Charbel Sakr, Naresh Shanbhag, Pavlo Molchanov, Michael B. Sullivan, Timothy Tsai, Steve Keckler
arXiv
Speculative Reconvergence for Improved SIMT Efficiency
Sana Damani, Daniel Johnson, Mark Stephenson, Eddie Yan, Olivier Giroux, Michael McKeown, Steve Keckler
International Symposium on Code Generation and Optimization
HMG: Extending Cache Coherence Protocols Across Modern Hierarchical Multi-GPU Systems
Xiaowei Ren, Daniel Lustig, Evgeny Bolotin, Aamer Jaleel, Oreste Villa, David Nellans
International Symposium on High Performance Computer Architecture (HPCA)

2019

Near-Memory Data Transformation for Efficient Sparse Matrix Multi-Vector Multiplication
Daichi Fujiki, Niladrish Chatterjee, Donghyuk Lee, Mike O'Connor
International Conference for High-Performance Computing, Networking, Storage, a…
MAGNet: A Modular Accelerator Generator for Neural Networks
Rangharajan Venkatesan, Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matt Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Yanqing Zhang, Brian Zimmer, William Dally, Joel Emer, Steve Keckler, Brucek Khailany
International Conference On Computer Aided Design (ICCAD)
Accelergy: An Architecture-Level Energy Estimation Methodology for Accelerator Designs
Yannan Nellie Wu, Joel Emer, Vivienne Sze
International Conference on Computer Aided Design (ICCAD)
Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture
Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Brucek Khailany, Steve Keckler
International Symposium on Microarchitecture (MICRO)
Best Paper award, IEEE Micro Top Picks in Computer Architecture (Honorable Mention)
ExTensor: An Accelerator for Sparse Tensor Algebra
Kartik Hegde, Hadi Asghari-Moghaddam, Michael Pellauer, Neal Crago, Aamer Jaleel, Edgar Solomonik, Joel Emer, Christopher W. Fletcher
International Symposium on Microarchitecture (MICRO)
IEEE Micro Top Picks in Computer Architecture (Honorable Mention)
Understanding Reuse, Performance, and Hardware Cost of DNN Dataflows: A Data-Centric Approach.
Hyoukjun Kwon, Prasanth Chatarasi, Michael Pellauer, Angshuman Parashar, Vivek Sarkar, Tushar Krishna
International Symposium on Microarchitecture (MICRO)
IEEE Micro Top Picks in Computer Architecture
NVBit: A Dynamic Binary Instrumentation Framework for NVIDIA GPUs
Oreste Villa, Mark Stephenson, David Nellans, Steve Keckler
International Symposium on Microarchitecture (MICRO)
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator Designed with a High-Productivity VLSI Methodology
Rangharajan Venkatesan, Sophia Shao, Brian Zimmer, Jason Clemons, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Steve Keckler, Brucek Khailany
Hot Chips: A Symposium on High Performance Chips
Optimizing Multi-GPU Parallelization Strategies for Deep Learning Training
Saptadeep Pal, Eiman Ebrahimi, Arslan Zulfiqar, Yaosheng Fu, Victor Zhang, Szymon Migacz, David Nellans, Puneet Gupta
IEEE MICRO: Special Edition on Machine Learning Acceleration
Optimizing Multi-GPU Parallelization Strategies for Deep Learning Training
Saptadeep Pal, Eiman Ebrahimi, Arslan Zulfiqar, Yaosheng Fu, Victor Zhang, Szymon Migacz, David Nellans, Puneet Gupta
arXiv
GPU Snapshot: Checkpoint Offloading for GPU-Dense Systems
Kyushick Lee, Michael B. Sullivan, Siva Hari, Timothy Tsai, Steve Keckler, Mattan Erez
International Conference on Supercomputing
On the Trend of Resilience for GPU-Dense Systems
Kyushick Lee, Michael B. Sullivan, Siva Hari, Timothy Tsai, Steve Keckler, Mattan Erez
International Conference on Dependable Systems and Networks, Supplemental (DSN-…
Best of SELSE (Workshop on Silicon Errors in Logic - System Effects)
Translation Ranger: Operating System Support for Contiguity-Aware TLBs
Zi Yan, Daniel Lustig, David Nellans, Abhishek Bhattacharjee
International Symposium on Computer Architecture (ISCA)
Adaptive Memory-Side Last-Level GPU Caching
Xia Zhao, Almutaz Adileh, Zhibin Yu, Zhiying Wang, Aamer Jaleel, Lieven Eeckhout
International Symposium on Computer Architecture (ISCA)
SNAP: A 1.67 – 21.55 TOPS/W Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference in 16nm CMOS
Jie-Fang Zhang, Ching-En Lee, Chester Liu, Yakun Sophia Shao, Steve Keckler, Zhengya Zhang
Symposia on VLSI Technology and Circuits (VLSI)
Buddy Compression: Enabling Larger Memory for Deep Learning and HPC Workloads on GPUs
Esha Choukse, Michael B. Sullivan, Mike O'Connor, Mattan Erez, Jeff Pool, David Nellans, Stephen W. Keckler
arXiv
Security Verification through Automatic Hardware-Aware Exploit Synthesis: The CheckMate Approach.
Caroline Trippel, Daniel Lustig, Margaret Martonosi
IEEE Micro (Issue: Top Picks of the 2018 Computer Architecture Conferences)
Nimble Page Management for Tiered Memory Systems
Zi Yan, Daniel Lustig, David Nellans, Abhishek Bhattacharjee
International Conference on Architectural Support for Programming Languages and…
A Formal Analysis of the NVIDIA PTX Memory Consistency Model.
Daniel Lustig, Sameer Sahasrabuddhe, Olivier Giroux
International Conference on Architectural Support for Programming Languages and…
IEEE Micro Top Picks in Computer Architecture (Honorable Mention)
Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration
Michael Pellauer, Yakun Sophia Shao, Jason Clemons, Neal Crago, Kartik Hegde, Rangharajan Venkatesan, Steve Keckler, Christopher W. Fletcher, Joel Emer
International Conference on Architectural Support for Programming Languages and…
IEEE Micro Top Picks in Computer Architecture (Honorable Mention)
DeLTA: GPU Performance Model for Deep Learning Applications with In-depth Memory System Traffic Analysis
Sangkug Lym, Donghyuk Lee, Mike O'Connor, Niladrish Chatterjee, Mattan Erez
arXiv
On the Trend of Resilience for GPU-Dense Systems
Kyushick Lee, Michael B. Sullivan, Siva Hari, Timothy Tsai, Steve Keckler, Mattan Erez
IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE)
Award paper
Towards Analytically Evaluating the Error Resilience of GPU Programs
Abdul Rehman Anwer, Guanpeng Li, Karthik Pattabiraman, Siva Hari, Michael B. Sullivan, Timothy Tsai
IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE)
DeLTA: GPU Performance Model for Deep Learning Applications with In-depth Memory System Traffic Analysis
Sankug Lym, Donghyuk Lee, Niladrish Chatterjee, Mike O'Connor, Mattan Erez
International Symposium on Performance Analysis of Systems and Software (ISPASS)
Timeloop: A Systematic Approach to DNN Accelerator Evaluation
Angshuman Parashar, Priyanka Raina, Yakun Sophia Shao, Yu-Hsin Chen, Victor A. Ying, Anurag Mukkara, Rangharajan Venkatesan, Brucek Khailany, Steve Keckler, Joel Emer
International Symposium on Performance Analysis of Systems and Software (ISPASS)
DUCATI: High-performance Address Translation by Extending TLB Reach of GPU-accelerated Systems
Aamer Jaleel, Eiman Ebrahimi, Sam Duncan
ACM Transactions on Architecture and Code Optimization (TACO)
Understanding the Future of Energy Efficiency in Multi-Module GPUs.
Akhil Arunkumar, Evgeny Bolotin, David Nellans, Carole-Jean Wu
International Symposium on High Performance Computer Architecture (HPCA)

2018

Optimizing Software-Directed Instruction Replication for GPU Error Detection
Abdulrahman Mahmoud, Siva Hari, Michael B. Sullivan, Timothy Tsai, Steve Keckler
International Conference for High-Performance Computing, Networking, Storage a…
Exploiting Idle Resources in a High-Radix Switch for Supplemental Storage
Matthias Blumrich, Ted Jiang, Larry Dennison
Proceedings of the International Conference for High Performance Computing, Net…
PipeProof: Automated Memory Consistency Proofs for Microarchitectural Specifications
Yatin A. Manerkar, Daniel Lustig, Margaret Martonosi, Aarti Gupta
International Symposium on Microarchitecture (MICRO)
IEEE Micro Top Picks in Computer Architecture (Honorable Mention), Best Paper nominee
SwapCodes: Error Codes for Hardware-Software Cooperative GPU Pipeline Error Detection
Michael B. Sullivan, Siva Hari, Brian Zimmer, Timothy Tsai, Stephen W. Keckler
The International Symposium on Microarchitecture (MICRO)
Harmonizing Speculative and Non-Speculative Execution in Architectures for Ordered Parallelism
Mark C. Jeffrey, Victor A. Ying, Suvinay Subramanian, Hyun Ryong Lee, Joel Emer, Daniel Sanchez
International Symposium on Microarchitecture (MICRO)
DAWG: A Defense Against Cache Timing Attacks in Speculative Execution Processors
Vladimir Kiriansky, Ilia Lebedev, Saman Amarasinghe, Srinivas Devadas, Joel Emer
International Symposium on Microarchitecture (MICRO)
CheckMate: Automated Synthesis of Hardware Exploits and Security Litmus Tests
Caroline Trippel, Daniel Lustig, Margaret Martonosi
International Symposium on Microarchitecture (MICRO)
IEEE Micro Top Picks in Computer Architecture
Combining HW/SW Mechanisms to Improve NUMA Performance of Multi-GPU Systems
Vinson Young, Aamer Jaleel, Evgeny Bolotin, Eiman Ebrahimi, David Nellans, Oreste Villa
International Symposium on Microarchitecture (MICRO)
Exposing Memory Access Patterns to Improve Instruction and Memory Efficiency in GPUs
Neal Crago, Mark Stephenson, Steve Keckler
ACM Transactions on Architecture and Code Optimization (TACO)
Software-Directed Techniques for Improved GPU Register File Utilization
Dani Voitsechov, Arslan Zulfiqar, Mark Stephenson, Mark Gebhart, Steve Keckler
ACM Transactions on Architecture and Code Optimization (TACO)
What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study
Saugata Ghose, Abdullah Giray Yağlıkçı, Raghav Gupta, Donghyuk Lee, Kais Kudrolli, William X. Liu, Hasan Hassan, Kevin K. Chang, Niladrish Chatterjee, Aditya Agrawal, Mike O'Connor, Onur Mutlu
arXiv
Modeling Soft Error Propagation in Programs
Guanpeng Li, Karthik Pattabiraman, Siva Hari, Michael B. Sullivan, Timothy Tsai
International Conference on Dependable Systems and Networks (DSN)
A Modular Digital VLSI Flow for High-Productivity SoC Design
Brucek Khailany, Evgeni Krimer, Rangharajan Venkatesan, Jason Clemons, Joel Emer, Matt Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Pinckney, Sophia Shao, Shreesha Srinath, Christopher Torng, Sam (Likun) Xi, Yanqing Zhang, Brian Zimmer
Design Automation Conference (DAC)
What Your DRAM Power Models Aren’t Telling You: Lessons from a Detailed Experimental Study
Saugata Ghose, Abdullah Giray Yağlıkçı, Raghav Gupta, Donghyuk Lee, Kais Kudrolli, William X. Liu, Hasan Hassan, Kevin Chang, Niladrish Chatterjee, Aditya Agrawal, Mike O'Connor, Onur Mutlu
ACM International Conference on Measurement and Analysis of Computer Systems (S…
The Locality Descriptor: A Holistic Cross-Layer Abstraction to Express Data Locality in GPUs
Nandita Vijayumar, Eiman Ebrahimi, Kevin Hsieh, Phillip B. Gibbons, Onur Mutlu
International Symposium on Computer Architecture (ISCA)
ACCORD: Enabling Associativity for Gigascale DRAM Caches by Coordinating Way-Install and Way-Prediction
Vinson Young, Chiachen Chou, Aamer Jaleel, Moinuddin Qureshi
International Symposium on Computer Architecture (ISCA)
A Case for Richer Cross-layer Abstractions: Bridging the Semantic Gap to Enhance Memory Optimization
Nandita Vijaykumar, Abhilasha Jain, Diptesh Majumdar, Kevin Hsieh, Gennady Pekhimenko, Eiman Ebrahimi, Nastaran Hajinazar, Phillip B. Gibbons, Onur Mutlu
International Symposium on Computer Architecture (ISCA)
UCNN: Exploiting Computational Reuse in Deep Neural Networks via Weight Repetition
Kartik Hegde, Jiyong Yu, Rohit Agrawal, Mengjia Yan, Michael Pellauer, Christopher W. Fletcher
International Symposium on Computer Architecture (ISCA)
Full-Stack Memory Model Verification with TriCheck
Caroline Trippel, Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi
IEEE Micro (Issue: Top Picks of the 2017 Computer Architecture Conferences)
Voltron: Understanding and Exploiting the Voltage-Latency-Reliability Trade-Offs in Modern DRAM Chips to Improve Energy Efficiency
Kevin K. Chang, Abdullah Giray Yağlıkçı, Saugata Ghose, Aditya Agrawal, Niladrish Chatterjee, Abhijith Kashyap, Donghyuk Lee, Mike O'Connor, Hasan Hassan, Onur Mutlu
arXiv
DUO: Exposing On-chip Redundancy to Rank-Level ECC for High Reliability
Seong-Lyong Gong, Jungrae Kim, Michael B. Sullivan, Howard David, Mattan Erez
International Symposium on High Performance Computer Architecture (HPCA)
Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks
Minsoo Rhu, Mike O'Connor, Niladrish Chatterjee, Jeff Pool, Youngeun Kwon, Steve Keckler
International Symposium on High Performance Computer Architecture (HPCA)
Reducing Data Transfer Energy by Exploiting Similarity within a Data Transaction
Donghyuk Lee, Mike O'Connor, Niladrish Chatterjee
International Symposium on High Performance Computer Architecture (HPCA)
Best Paper nominee
Stitch-X: An Accelerator Architecture for Exploiting Unstructured Sparsity in Deep Neural Networks
Ching-En Lee, Yakun Sophia Shao, Jie-Fang Zhang, Angshuman Parashar, Joel Emer, Steve Keckler, Zhengya Zhang
SysML Conference
MeltdownPrime and SpectrePrime: Automatically-Synthesized Attacks Exploiting Invalidation-Based Coherence Protocols
Caroline Trippel, Daniel Lustig, Margaret Martonosi
arXiv

2017

Toward Standardized Near-Data Processing with Unrestricted Data Placement for GPUs
Gwangsun Kim, Niladrish Chatterjee, Mike O'Connor, Kevin Hsieh
International Conference for High-Performance Computing, Networking, Storage, a…
Understanding Error Propagation in Deep Learning Neural Network (DNN) Accelerators and Applications
Guanpeng Li, Siva Hari, Michael B. Sullivan, Timothy Tsai, Karthik Pattabiraman, Joel Emer, Steve Keckler
The International Conference for High Performance Computing, Networking, Storag…
Fine-Grained DRAM: Energy-Efficient DRAM for Extreme Bandwidth Systems
Mike O'Connor, Niladrish Chatterjee, Donghyuk Lee, John Wilson, Aditya Agrawal, Steve Keckler, William Dally
International Symposium on Microarchitecture (MICRO)
Xylem: Enhancing Vertical Thermal Conduction in 3D Processor-Memory Stacks
Aditya Agrawal, Josep Torrellas, Sachin Idgunji
International Symposium on Microarchitecture (MICRO)
Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology
Vivek Seshadri, Donghyuk Lee, Thomas Mullins, Hasan Hassan, Amirali Boroumand, Jeremie Kim, Michael A. Kozuch, Onur Mutlu, Phillip B. Gibbons, Todd C. Mowry
International Symposium on Microarchitecture (MICRO)
Detecting and Mitigating Data-Dependent DRAM Failures by Exploiting Current Memory Content
Samira Khan, Chris Wilkerson, Zhe Wang, Alaa R. Alameldeen, Donghyuk Lee, Onur Mutlu
International Symposium on Microarchitecture (MICRO)
RTLCheck: Verifying Memory Consistency in RTL Designs
Yatin A. Manerkar, Daniel Lustig, Margaret Martonosi, Michael Pellauer
International Symposium on Microarchitecture (MICRO)
IEEE Micro Top Picks in Computer Architecture (Honorable Mention)
Beyond the Socket: NUMA-Aware GPUs
Ugljesa Milic, Oreste Villa, Evgeny Bolotin, Akhil Arunkumar, Eiman Ebrahimi, Aamer Jaleel, Alex Ramirez, David Nellans
International Symposium on Microarchitecture (MICRO)
Weak Memory Models with Matching Axiomatic and Operational Definitions
Sizhuo Zhang, Muralidaran Vijayaraghavan, Daniel Lustig, Arvind
arXiv
BATMAN: Maximizing Bandwidth Utilization of Hybrid Memory Systems
Chiachen Chou, Aamer Jaleel, Moinuddin Qureshi
International Symposium on Memory Systems (MEMSYS)
MCM-GPU: Multi-Chip-Module GPUs for Continued Performance Scalability
Akhil Arunkumar , Evgeny Bolotin, Benjamin Cho, Ugljesa Milic , Eiman Ebrahimi, Oreste Villa, Aamer Jaleel, Carole-Jean Wu , David Nellans
International Symposium on Computer Architecture (ISCA)
SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks
Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel Emer, Steve Keckler, William Dally
International Symposium on Computer Architecture (ISCA)
Fractal: An Execution Model for Fine-Grain Nested Speculative Parallelism
Suvinay Subramanian, Mark C. Jeffrey, Maleen Abeydeera, Hyun Ryong Lee, Victor A. Ying, Joel Emer, Daniel Sanchez
International Symposium on Computer Architecture (ISCA)
Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms
Donghyuk Lee, Samira Khan, Lavanya Subramanian, Saugata Ghose, Rachata Ausavarungnirun, Gennady Pekhimenko, Vivek Seshadri, Onur Mutlu
ACM Conference on Measurement and Analysis of Computer Systems (SIGMETRICS 2017)
Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms
Kevin Chang, Abdullah Giray Yağlıkçı, Saugata Ghose, Aditya Agrawal, Niladrish Chatterjee, Abhijith Kashyap, Donghyuk Lee, Mike O'Connor, Hasan Hassan, Onur Mutlu
ACM Conference on Measurement and Analysis of Computer Systems (SIGMETRICS 2017)
Understanding Reduced-Voltage Operation in Modern DRAM Chips: Characterization, Analysis, and Mechanisms
Kevin K. Chang, Abdullah Giray Yağlıkçı, Saugata Ghose, Aditya Agrawal, Niladrish Chatterjee, Abhijith Kashyap, Donghyuk Lee, Mike O'Connor, Hasan Hassan, Onur Mutlu
arXiv
SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks
Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel Emer, Steve Keckler, William Dally
arXiv
Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks
Minsoo Rhu, Mike O'Connor, Niladrish Chatterjee, Jeff Pool, Stephen W. Keckler
arXiv
SASSIFI: An Architecture-level Fault Injection Tool for GPU Application Resilience Evaluation
Siva Hari, Timothy Tsai, Mark Stephenson, Steve Keckler, Joel Emer
International Symposium on Performance Analysis of Systems and Software (ISPASS)
Automated Synthesis of Comprehensive Memory Model Litmus Test Suites
Daniel Lustig, Andrew Wright, Alexandros Papakonstantinou, Olivier Giroux
International Conference on Architectural Support for Programming Languages and…
TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA
Caroline Trippel, Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi
International Conference on Architectural Support for Programming Languages and…
IEEE Micro Top Picks in Computer Architecture
SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies
Hasan Hassan, Nandita Vijaykumar, Samira Khan, Saugata Ghose, Kevin Chang, Gennady Pekhimenko, Donghyuk Lee, Oguz Ergin, Onur Mutlu
International Symposium on High Performance Computer Architecture (HPCA)
Architecting an Energy-Efficient DRAM System for GPUs
Niladrish Chatterjee, Mike O'Connor, Donghyuk Lee, Daniel Johnson, Minsoo Rhu, Steve Keckler, William Dally
International Symposium on High Performance Computer Architecture (HPCA)

2016

Counterexamples and Proof Loophole for the C/C++ to POWER and ARMv7 Trailing-Sync Compiler Mappings
Yatin A. Manerkar, Caroline Trippel, Daniel Lustig, Michael Pellauer, Margaret Martonosi
arXiv
Snatch: Opportunistically Reassigning Power Allocation between Processor and Memory in 3D Stacks
Dimitrios Skarlatos, Renji Thomas, Aditya Agrawal, Shibin Qin, Robert Pilawa-Podgurski, Ulya R. Karpuzcu, Radu Teodorescu, Nam Sung Kim, Josep Torrellas
International Symposium on Microarchitecture (MICRO)
CANDY: Enabling Coherent DRAM Caches for Multi-Node Systems
Chiachen Chou, Aamer Jaleel, Moinuddin Qureshi
International Symposium on Microarchitecture (MICRO)
Approxilyzer: Towards A Systematic Framework for Instruction-Level Approximate Computing and its Application to Hardware Resiliency
Radha Venkatagiri, Abdulrahman Mahmoud, Siva Hari, Sarita Adve
International Symposium on Microarchitecture (MICRO)
The Bunker Cache for Spatio-Value Approximation
Joshua San Miguel, Jorge Albericio, Aamer Jaleel, Natalie Enright Jerger
International Symposium on Microarchitecture (MICRO)
vDNN: Virtualized Deep Neural Networks for Scalable, Memory-Efficient Neural Network Design.
Minsoo Rhu, Natalia Gimelshein, Jason Clemons, Arslan Zulfiqar, Steve Keckler
International Symposium on Microarchitecture (MICRO)
Data-Centric Execution of Speculative Parallel Programs
Mark C. Jeffrey, Suvinay Subramanian, Maleen Abeydeera, Joel Emer, Daniel Sanchez
International Symposium on Microarchitecture (MICRO)
Co-Designing Accelerators and SoC Interfaces Using gem5-Aladdin
Yakun Sophia Zhao, Sam (Likun) Xi, Vijayalakshmi Srinivasan, Gu-Yeon Wei, David Brooks
International Symposium on Microarchitecture (MICRO)
A Patch Memory System For Image Processing and Computer Vision.
Jason Clemons, Chih-Chi Cheng, Iuri Frosio, Daniel Johnson, Steve Keckler
International Symposium on Microarchitecture (MICRO)
CLARA: Circular Linked-List Auto- and Self-Refresh Architecture
Aditya Agrawal, Mike O'Connor, Evgeny Bolotin, Niladrish Chatterjee, Joel Emer, Steve Keckler
International Symposium on Memory Systems (MEMSYS'16)
Automatically Exploiting Implicit Pipeline Parallelism from Multiple Dependent Kernels for GPUs
Gwangsun Kim, Jiyun Jeong, John Kim, Mark Stephenson
International Conference on Parallel Architectures and Compilation (PACT)
TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA
Caroline Trippel, Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi
arXiv
Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks
Yu-Hsin Chen, Joel Emer, Vivienne Sze
International Symposium on Computer Architecture (ISCA)
EIE: Efficient Inference Engine on Compressed Deep Neural Network
Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark Horowitz, William Dally
International Symposium on Computer Architecture (ISCA)
Accelerating Dependent Cache Misses with an Enhanced Memory Controller
Milad Hashemi, Khubaib, Eiman Ebrahimi, Onur Mutlu, Yale N. Patt
International Symposium on Computer Architecture (ISCA)
LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches
Hsiang-Yun Cheng, Jishen Zhao, Jack Sampson, Mary Jane Irwin, Aamer Jaleel, Yu Lu, Yuan Xie
International Symposium on Computer Architecture (ISCA)
Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems
Kevin Hsieh, Eiman Ebrahimi, Gwangsun Kim, Niladrish Chatterjee, Mike O'Connor, Nandita Vijaykumar, Onur Mutlu, Steve Keckler
International Symposium on Computer Architecture (ISCA)
Bit-Plane Compression: Transforming Data for Better Compression in Many-core Architectures
Jungrae Kim, Michael B. Sullivan, Esha Choukse, Mattan Erez
The International Symposium on Computer Architecture (ISCA)
A Real-time Energy-Efficient Superpixel Hardware Accelerator for Mobile Computer Vision Applications
Injoon Hong, Jason Clemons, Rangharajan Venkatesan, Iuri Frosio, Brucek Khailany, Steve Keckler
Design Automation Conference (DAC)
All-Inclusive ECC: Thorough End-to-End Protection for Reliable Computer Memory
Jungrae Kim, Michael B. Sullivan, Sangkug Lym, Mattan Erez
The International Symposium on Computer Architecture (ISCA)
Towards High Performance Paged Memory for GPUs
Tianhao Zheng, David Nellans, Arslan Zulfiqar, Mark Stephenson, Steve Keckler
International Symposium on High Performance Computer Architecture (HPCA)
Selective GPU Caches to Eliminate CPU-GPU HW Cache Coherence
Neha Agarwal, David Nellans, Eiman Ebrahimi, Thomas F. Wenisch, John Danskin, Steve Keckler
International Symposium on High Performance Computer Architecture (HPCA)
A Case for Toggle-Aware Compression for GPU Systems
Gennady Pekhimenko, Evgeny Bolotin, Nandita Vijaykumar, Onur Mutlu, Todd C. Mowry, Steve Keckler
International Symposium on High Performance Computer Architecture (HPCA)
An Analytical Model for Hardened Latch Selection and Exploration
Michael B. Sullivan, Brian Zimmer, Siva Hari, Timothy Tsai, Steve Keckler
Workshop on Silicon Errors in Logic--System Effects (SELSE)
vDNN: Virtualized Deep Neural Networks for Scalable, Memory-Efficient Neural Network Design
Minsoo Rhu, Natalia Gimelshein, Jason Clemons, Arslan Zulfiqar, Steve Keckler
arXiv

2015

A Scalable Architecture for Ordered Parallelism
Mark C. Jeffery, Suvinay Subramanian, Cong Yang, Joel Emer, Daniel Sanchez
International Symposium on Microarchitecture (MICRO)
A Fast and Accurate Analytical Technique to Compute the AVF of Sequential Bits in a Processor
Steve Raasch, Arijis Biswas, Jon Stephan, Paul Racunas, Joel Emer
International Symposium on Microarchitecture (MICRO)
CCICheck: Using μhb Graphs to Verify the Coherence-Consistency Interface
Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi
International Symposium on Microarchitecture (MICRO)
Exploiting Asymmetry in Booth-Encoded Multipliers for Reduced Energy Multiplication
Mike O'Connor, Earl Swartzlander, Jr.
49th Asilomar Conference on Signals, Systems, and Computers
Anatomy of GPU Memory System for Multi-Application Execution
Adwait Jog, Onur Kayiran, Tuba Kesten, Ashutosh Pattnaik, Evgeny Bolotin, Niladrish Chatterjee, Steve Keckler, Mahmut T. Kandemir, Chita R. Das
International Symposium on Memory Systems (MEMSYS)
GPU Computing Pipeline Inefficiencies and Optimization Opportunities in Heterogeneous CPU-GPU Processors
Joel Hestness, Steve Keckler, David A. Wood
International Symposium on Workload Characterization (IISWC)
Scavenger: Automating the Construction of Application-Optimized Memory Hierarchies
Hsin-Jung Yang, Kermin Fleming, Michael Adler, Felix Winterstein, Joel Emer
International Conference on Field Programmable Logic and Applications (FPL)
Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures
Michael Pellauer, Angshuman Parashar, Michael Adler, Bushra Ahsan, Randy Almon, Neal Crago, Kermin Fleming, Mohit Gambhir, Aamer Jaleel, Tushar Krishna, Daniel Lustig, Stephen Maresh, Vladimir Pavlov, Rachid Rayess, Antonia Zhai, Joel Emer
ACM Transactions on Computing Systems (TOCS)
MemcachedGPU: Scaling-up Scale-out Key-value Stores
Tayler Hetherington, Mike O'Connor, Tor Aamodt
Sixth ACM Symposium on Cloud Computing (SoCC '15)
Designing Efficient Heterogeneous Memory Architectures
Evgeny Bolotin, David Nellans, Oreste Villa, Mike O'Connor, Alex Ramirez, Steve Keckler, Mike O'Connor
IEEE Micro
A Variable Warp Size Architecture
Timothy Rogers, Daniel Johnson, Mike O'Connor, Steve Keckler
International Symposium on Computer Architecture (ISCA)
Flexible Software Profiling of GPU Architectures
Mark Stephenson, Siva Hari, Yunsup Lee, Eiman Ebrahimi, Daniel Johnson, David Nellans, Mike O'Connor, Steve Keckler
International Symposium on Computer Architecture (ISCA)
Locality-Driven Dynamic GPU Cache Bypassing
Chao Li, Shuaiwen Leon Song, Hongwen Dai, Siva Hari, Albert Sidelnik, Huiyang Zhou
International Conference on Supercomputing (ICS)
Toggle-aware Compression for GPUs
Gennady Pekhimenko, Evgeny Bolotin, Mike O'Connor, Onur Mutlu, Todd C. Mowry, Steve Keckler
IEEE Computer Architecture Letters ( Volume: 14, Issue: 2, July-Dec. 1 2015 )
SASSIFI: Evaluating Resilience of GPU Applications
Siva Hari, Timothy Tsai, Mark Stephenson, Steve Keckler, Joel Emer
Workshop on Silicon Errors in Logic - System Effects (SELSE-11)
In-Memory Graph Databases for Web-Scale Data
Vito Giovanni Castellana, Alessandro Morari, Jesse Weaver, Antonino Time, David Haglin, Oreste Villa, John Feo
IEEE Computer
Page Placement Strategies for GPUs within Heterogeneous Memory Systems
Neha Agarwal, David Nellans, Mark Stephenson, Mike O'Connor, Steve Keckler
International Conference on Architectural Support for Programming Languages and…
Priority-Based Cache Allocation in Throughput Processors
Dong Li, Minsoo Rhu, Daniel Johnson, Mike O'Connor, Mattan Erez, Donald Fussell, Steve Keckler
International Symposium on High Performance Computer Architecture (HPCA)
High Performing Cache Hierarchies for Server Workloads -- Relaxing Inclusion to Capture the Latency Benefits of Exclusive Caches
Aamer Jaleel, Joseph Nuzman, Adrian Moga, Simon C. Steely Jr., Joel Emer
International Symposium on High Performance Computer Architecture (HPCA)
Unlocking Bandwidth for GPUs in CC-NUMA systems
Neha Agarwal, David Nellans, Mike O'Connor, Steve Keckler, Thomas Wenisch
International Symposium on High Performance Computer Architecture (HPCA)

2014

Arbitrary Modulus Indexing
Jeffrey R. Diamond, Donald S. Fussell, Steve Keckler
International Symposium on Microarchitecture (MICRO)
Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures
Yunsup Lee, Vinod Grover, Ronny Krashinsky, Mark Stephenson, Steve Keckler, Krste Asanovic
International Symposium on Microarchitecture (MICRO)
Scaling the Power Wall: A Path to Exascale
Oreste Villa, Daniel Johnson, Mike O'Connor, Evgeny Bolotin, David Nellans, Justin Luitjens, Nikolai Sakharnykh, Peng Wang, Paulius Micikevicius, Anthony Scudiero, Steve Keckler, William Dally
SC '14
A Comparative Analysis of Microarchitecture Effects on CPU and GPU Memory System Behavior
Joel Hestness, Steve Keckler, David A. Wood
International Symposium on Workload Characterization (IISWC)
Scaling Irregular Applications through Data Aggregation and Software Multithreading
Alessandro Morari, Antonino Tumeo, Daniel Chavarria-Miranda, Oreste Villa, Mateo Valero
International Parallel and Distributed Processing Symposium (IPDPS)
Measuring the Radiation Reliability of SRAM Structures in GPUs Designed for HPC
Paolo Rech, Luigi Carro, Nicholas Wang, Timothy Tsai, Siva Hari, Steve Keckler
Workshop on Silicon Errors in Logic - System Effects (SELSE-10)
Application-aware Memory System for Fair and Efficient Execution of Concurrent GPGPU Applications
Adwait Jog, Evgeny Bolotin, Zvika Guz, Mike Parker, Steve Keckler, Mahmut T. Kandemir, Chita R. Das
Workshop on General Purpose Processing Using GPUs (GPGPU-7)

2013

21st Century Digital Design Tools
William Dally, Chris Malachosky, Steve Keckler
Design Automation Conference (DAC)
Convergence and Scalarization for Data-Parallel Architectures
Yunsup Lee, Ronny Krashinsky, Vinod Grover, Steve Keckler, Krste Asanovic
International Symposium on Code Generation and Optimization (CGO)

2012

Unifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor
Mark Gebhart, Steve Keckler, Brucek Khailany, Ronny Krashinsky, William Dally
International Symposium on Microarchitecture (MICRO)
A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput Processors
Mark Gebhart, Daniel R. Johnson, David Tarjan, Steve Keckler, William Dally, Erik Lindholm, Kevin Skadron
ACM Transactions on Computer Systems (TOCS)

2011

A Compile-Time Managed Multi-Level Register File Hierarchy
Mark Gebhart, Steve Keckler, William Dally
International Symposium on Microarchitecture (MICRO)
CudaDMA: Optimizing GPU Memory Bandwidth via Warp Specialization
Michael Bauer, Henry Cook, Brucek Khailany
SC '11
GPUs and the Future of Parallel Computing
Steve Keckler, William Dally, Brucek Khailany, Michael Garland, David Glasco
IEEE Micro
Energy-efficient Mechanisms for Managing Thread Context in Throughput Processors
Mark Gebhart, Daniel R. Johnson, David Tarjan, Steve Keckler, William Dally, Erik Lindholm, Kevin Skadron
International Symposium on Computer Architecture (ISCA)

2009

Increasing Memory Miss Tolerance for SIMD Cores
David Tarjan, Jiayuan Meng, Kevin Skadron
International Conference for High Performance Computing, Networking, Storage an…

2007

The NVIDIA GeForce 8800 GPU
Erik Lindholm, Stuart Oberman
2007 IEEE Hot Chips 19 Symposium

Researchers

Aamer Jaleel
Ben Keller
Benjamin Klenk
Bob Alfieri
Brucek Khailany
Daniel Lustig
David Nellans
Dennis Abts
Erik Lindholm
Evgeny Bolotin
Guillermo Marcus
Hans Eberle
Harini Muthukrishnan
Isaac Gelado
Josef Spjut
Mark Stephenson
Matthias Blumrich
Matthijs Van keirsbilck
Michael Pellauer
Mike Sullivan
Mohamed Tarek Ibn Ziad
Nathaniel Pinckney
Nicolai Oswald
Oreste Villa
Po-An Tsai
Qijing Jenny Huang
Rangharajan Venkatesan
Sana Damani
Siva Hari
Song Han
Steve Keckler
Timothy Tsai
Vignesh Balaji
Vinu Joseph
Wen-mei Hwu
William Dally
Yaosheng Fu