Computer Architecture

Associated Publications

Optimizing Software-Directed Instruction Replication for GPU Error Detection
Kayotee: A Fault Injection-based System to Assess the Safety and Reliability of Autonomous Vehicles to Faults and Errors
A Modular Digital VLSI Flow for High-Productivity SoC Design
Reducing Data Transfer Energy by Exploiting Similarity within a Data Transaction
Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks
Toward Standardized Near-Data Processing with Unrestricted Data Placement for GPUs
Understanding Error Propagation in Deep Learning Neural Network (DNN) Accelerators and Applications
Fine-Grained DRAM: Energy-Efficient DRAM for Extreme Bandwidth Systems
Beyond the socket: NUMA-aware GPUs
MCM-GPU: Multi-Chip-Module GPUs for Continued Performance Scalability
SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks
Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms
Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms
SASSIFI: An Architecture-level Fault Injection Tool for GPU Application Resilience Evaluation
Automated Synthesis of Comprehensive Memory Model Litmus Test Suites
TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA
Architecting an Energy-Efficient DRAM System for GPUs
Approxilyzer: Towards A Systematic Framework for Instruction-Level Approximate Computing and its Application to Hardware Resiliency
CLARA: Circular Linked-List Auto- and Self-Refresh Architecture
Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems
A Real-time Energy-Efficient Superpixel Hardware Accelerator for Mobile Computer Vision Applications
All-Inclusive ECC: Thorough End-to-End Protection for Reliable Computer Memory
A Case for Toggle-Aware Compression for GPU Systems
An Analytical Model for Hardened Latch Selection and Exploration
Exploiting Asymmetry in Booth-Encoded Multipliers for Reduced Energy Multiplication
Anatomy of GPU Memory System for Multi-Application Execution
MemcachedGPU: Scaling-up Scale-out Key-value Stores
Designing Efficient Heterogeneous Memory Architectures
Flexible Software Profiling of GPU Architectures
A Variable Warp Size Architecture
Toggle-aware Compression for GPUs
Page Placement Strategies for GPUs within Heterogeneous Memory Systems
Unlocking Bandwidth for GPUs in CC-NUMA systems
Priority-Based Cache Allocation in Throughput Processors
Scaling the Power Wall: A Path to Exascale
Application-aware Memory System for Fair and Efficient Execution of Concurrent GPGPU Applications
Unifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor
A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput Processors
A Compile-Time Managed Multi-Level Register File Hierarchy
Energy-efficient Mechanisms for Managing Thread Context in Throughput Processors
Increasing Memory Miss Tolerance for SIMD Cores