Computer Architecture

Associated Publications

PyTorchFI: A Runtime Perturbation Tool for DNNs
Buddy Compression: Enabling Larger Memory for Deep Learning and HPC Workloads on GPUs
Estimating Silent Data Corruption Rates Using a Two-Level Model
Feature Map Vulnerability Evaluation in CNNS
Near-Memory Data Transformation for Efficient Sparse Matrix Multi-Vector Multiplication
MAGNet: A Modular Accelerator Generator for Neural Networks
NVBit: A Dynamic Binary Instrumentation Framework for NVIDIA GPUs
Simba: Scaling Deep-Learning Inference withMulti-Chip-Module-Based Architecture
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator Designed with a High-Productivity VLSI Methodology
GPU Snapshot: Checkpoint Offloading for GPU-Dense Systems
ML-based Fault Injection for Autonomous Vehicles: A Case for Bayesian Fault Injection
On the Trend of Resilience for GPU-Dense Systems
DeLTA: GPU Performance Model for Deep Learning Applications with In-depth Memory System Traffic Analysis
Optimizing Software-Directed Instruction Replication for GPU Error Detection
Exploiting Idle Resources in a High-Radix Switch for Supplemental Storage
Kayotee: A Fault Injection-based System to Assess the Safety and Reliability of Autonomous Vehicles to Faults and Errors
SwapCodes: Error Codes for Hardware-Software Cooperative GPU Pipeline Error Detection
Exposing Memory Access Patterns to Improve Instruction and Memory Efficiency in GPUs
Software-Directed Techniques for Improved GPU Register File Utilization
A Modular Digital VLSI Flow for High-Productivity SoC Design
What Your DRAM Power Models Aren’t Telling You: Lessons from a Detailed Experimental Study
Reducing Data Transfer Energy by Exploiting Similarity within a Data Transaction
Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks
Toward Standardized Near-Data Processing with Unrestricted Data Placement for GPUs
Understanding Error Propagation in Deep Learning Neural Network (DNN) Accelerators and Applications
Fine-Grained DRAM: Energy-Efficient DRAM for Extreme Bandwidth Systems
Beyond the Socket: NUMA-Aware GPUs
SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks
MCM-GPU: Multi-Chip-Module GPUs for Continued Performance Scalability
Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms
Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms
SASSIFI: An Architecture-level Fault Injection Tool for GPU Application Resilience Evaluation
TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA
Automated Synthesis of Comprehensive Memory Model Litmus Test Suites
Architecting an Energy-Efficient DRAM System for GPUs
Approxilyzer: Towards A Systematic Framework for Instruction-Level Approximate Computing and its Application to Hardware Resiliency
CLARA: Circular Linked-List Auto- and Self-Refresh Architecture
Automatically Exploiting Implicit Pipeline Parallelism from Multiple Dependent Kernels for GPUs
Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems
A Real-time Energy-Efficient Superpixel Hardware Accelerator for Mobile Computer Vision Applications
All-Inclusive ECC: Thorough End-to-End Protection for Reliable Computer Memory
A Case for Toggle-Aware Compression for GPU Systems
An Analytical Model for Hardened Latch Selection and Exploration
Exploiting Asymmetry in Booth-Encoded Multipliers for Reduced Energy Multiplication
Anatomy of GPU Memory System for Multi-Application Execution
MemcachedGPU: Scaling-up Scale-out Key-value Stores
Designing Efficient Heterogeneous Memory Architectures
A Variable Warp Size Architecture
Flexible Software Profiling of GPU Architectures
Toggle-aware Compression for GPUs
Page Placement Strategies for GPUs within Heterogeneous Memory Systems
Priority-Based Cache Allocation in Throughput Processors
Unlocking Bandwidth for GPUs in CC-NUMA systems
Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures
Scaling the Power Wall: A Path to Exascale
Application-aware Memory System for Fair and Efficient Execution of Concurrent GPGPU Applications
Unifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor
A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput Processors
A Compile-Time Managed Multi-Level Register File Hierarchy
Energy-efficient Mechanisms for Managing Thread Context in Throughput Processors
Increasing Memory Miss Tolerance for SIMD Cores
The NVIDIA GeForce 8800 GPU