Snatch: Opportunistically Reassigning Power Allocation between Processor and Memory in 3D Stacks

The pin count largely determines the cost of a chip package, which is often comparable to the cost of a die. In 3D processor-memory designs, power and ground (P/G) pins can account for the majority of the pins. This is because packages include separate pins for the disjoint processor and memory power delivery networks (PDNs). Supporting separate PDNs and P/G pins for processor and memory is inefficient, as each set has to be provisioned for the worst-case power delivery requirements. In this paper, we propose to reduce the number of P/G pins of both processor and memory in a 3D design, and dynamically and opportunistically divert some power between the two PDNs on demand. To perform the power transfer, we use a small bidirectional on-chip voltage regulator that connects the two PDNs. Our concept, called Snatch, is effective. It allows the computer to execute code sections with high processor or memory power requirements without having to throttle performance. We evaluate Snatch with simulations of an 8-core multicore stacked with two memory dies. In a set of compute-intensive codes, the processor snatches memory power for 30% of the time on average, speeding-up the codes by up to 23% over advanced turbo-boosting; in memory-intensive codes, the memory snatches processor power. Alternatively, Snatch can reduce the package cost by about 30%.


Dimitrios Skarlatos (University of Illinois at Urbana-Champaign)
Renji Thomas (Ohio State University)
Aditya Agrawal (NVIDIA)
Shibin Qin (University of Illinois at Urbana-Champaign)
Robert Pilawa-Podgurski (University of Illinois at Urbana-Champaign)
Ulya R. Karpuzcu (University of Minnesota - Twin Cities)
Radu Teodorescu (Ohio State University)
Nam Sung Kim (University of Illinois at Urbana-Champaign)
Josep Torrellas (University of Illinois at Urbana-Champaign)

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