Research Areas

VS-QUANT: Per-Vector Scaled Quantization for Accurate Low-Precision Neural Network Inference

To be published at Design Automation Conference 2021 (Preprints)

Steve Dai

Ground-Referenced Single-Ended Signaling: Applications for High-Density Short-Haul Communication Systems

MLSys 2021

John Wilson

Walker Turner

John Poulton

Solid-State Circuits Magazine

MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification

Vidya A. Chhabria

Sachin S. Sapatnekar

2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)

Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization

Mingjie Liu

Walker Turner

George Kokai

David Z. Pan

NVCell: Generate Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning

2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)

2020

How Software Can "Chip In" to the IC Design Process: A Multidisciplinary Approach May Attract New Talent and Accelerate Innovation

Workshop on ML for Systems at NeurIPS

Alicia Klinefelter

IEEE Solid-State Circuits Magazine

Accelerating Chip Design with Machine Learning

Saad Godil

Robert Kirby

Alicia Klinefelter

Bryan Catanzaro

IEEE Micro

ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks

George Kokai

Walker Turner

Ting-Sheng Ku

Design Automation Conference (DAC) 2020

GRANNITE: Graph Neural Network Inference for Transferable Power Estimation

Design Automation Conference (DAC) 2020

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement

Yibo Lin

Zixuan Jiang

Jiaqi Gu

Wuxi Li

Shounak Dhar

ABCDPlace: Accelerated Batch-based Concurrent Detailed Placement on Multi-threaded CPUs and GPUs

David Z. Pan

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)

Reference-Noise Compensation Scheme for Single- Ended Package-to-Package Links

2020 International Solid-State Circuits Conference

Yibo Lin

Wuxi Li

Jiaqi Gu

A 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm

David Z. Pan

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)

PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network

Yakun Sophia Shao

Alicia Klinefelter

Priyanka Raina

IEEE Journal of Solid-State Circuits (JSSC)

Zhiyao Xie

FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning

Ye Sheng

Santosh Santosh

Jiang Hu

Yiran Chen

ASP-DAC 2020

Zhiyao Xie

Guan-Qi Fang

Yu-Hung Huang

Shao-Yun Fang

Jiang Hu

Yiran Chen

Erick Carvajal Barboza

ASP-DAC 2020

2019

MAGNet: A Modular Accelerator Generator for Neural Networks

Sophia Shao

Miaorong Wang

Alicia Klinefelter

Priyanka Raina

International Conference On Computer Aided Design

Simba: Scaling Deep-Learning Inference withMulti-Chip-Module-Based Architecture

Sophia Shao

Jason Clemons

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator Designed with a High-Productivity VLSI Methodology

Alicia Klinefelter

Priyanka Raina

52nd IEEE/ACM International Symposium on Microarchitecture

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm

Sophia Shao

Alicia Klinefelter

Priyanka Raina

Hot Chips: A Symposium on High Performance Chips

Sophia Shao

Alicia Klinefelter

Priyanka Raina

Symposium on VLSI Circuits Digest of Technical Papers

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement

Yibo Lin

Shounak Dhar

Wuxi Li

David Z. Pan

Design Automation Conference (DAC) 2019

Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference

Angad S. Rekhi

Nikola Nedovic

Nigxi Liu

Miaorong Wang

Design Automation Conference (DAC)

PRIMAL: Power Inference using Machine Learning

Yuan Zhou

Zhiru Zhang

Design Automation Conference (DAC)

High Performance Graph Convolutional Networks with Applications in Testability Analysis

Yuzhe Ma

Harbinder Sikka

Lijuan Luo

Karthikeyan Natarajan

Bei Yu

Design Automation Conference (DAC)

A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET

Alicia Klinefelter

Tezaswi Raja

Kevin Zhou

Voltage-Follower Coupling Quadrature Oscillator with Embedded Phase-Interpolator in 16nm FinFET

ASYNC 2019

IEEE Custom Integrated Circuits Conference 2019

Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model

Yu-Hung Huang

Zhiyao Xie

Guan-Qi Fang

Tao-Chun Yu

A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator

Shao-Yun Fang

Yiran Chen

Jiang Hu

Design, Automation and Test in Europe

Wenxu Zhao

Sunil Sudhakaran

RouteNet: Routability Prediction for Mixed-size Designs using Convolutional Neural Network

IEEE JOURNAL OF SOLID-STATE CIRCUITS

2018

Zhiyao Xie

Yu-Hung Huang

Guan-Qi Fang

Shao-Yun Fang

Yiran Chen

Hu Jiang

International Conference On Computer Aided Design

A Modular Digital VLSI Flow for High-Productivity SoC Design

Evgeni Krimer

Alicia Klinefelter

Sophia Shao

Shreesha Srinath

Christopher Torng

Sam (Likun) Xi

A Switching Linear Regulator Based on a Fast-Self-Clocked Comparator with Very Low Probability of Meta-stability and a Parallel Analog Ripple Control Module

Design Automation Conference (DAC)

Hardware-Enabled Artificial Intelligence

Symposia on VLSI Technology and Circuits

Wenxu Zhao

Custom Integrated Circuits Conference

Ground-Referenced Signaling for Intra-Chip and Short-Reach Chip-to-Chip Interconnects

Sunil Sudhakaran

Rizwan Bashirullah

Wenxu Zhao

A 1.17pJ/b 25Gb/s/pin Ground-Referenced Single Ended Serial Link for Off- and On-Package Communication in 16nm CMOS Using a Process- and Temperature-Adaptive Voltage Regulator

Custom Integrated Circuits Conference

Wenxu Zhao

Sunil Sudhakaran

Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks

ISSCC

2016

Divya Akella Kamakshi

A 6.5-to-23.3fJ/b/mm Balanced Charge-Recycling Bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with Clock Forwarding and Low-Crosstalk Contraflow Wiring

Sudhir Kudva

Yaping Zhou

Benton H. Calhoun

ASYNC 2016

Hybrid Modulation for Near Zero Display Latency

Trey Greer

Josef Spjut

David Luebke

Turner Whitted

Current parking regulator for zero droop/overshoot load transient response

Applied Power Electronics Conference and Exposition (APEC)

International Solid-State Circuits Conference (ISSCC 2016)

A 28nm 2Mbit 6T SRAM with Highly Configurable Write Assist Implementation and Capacitor Based Sense Amplifier Input Offset Compen

Mahmut Sinangil

Andy Gotterba

Jesse Wang

Jason Golbus

Journal of Solid State Circuits

2015

A Pausible Bisynchronous FIFO for GALS Systems

Ben Keller

ASYNC 2015

High-speed Low-power On-chip Global Signaling Design Overview

Rizwan Bashirullah

DesignCon

2014

A Reverse Write Assist Circuit for SRAM Dynamic Write VMIN Tracking using Canary SRAMs

Arijit Banerjee

Mahmut Sinangil

John Poulton

A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications

Ben Calhoun

International Symposium on Quality Electronic Design

2013

John Eyles

Journal of Solid State Circuits

A 0.54pJ/b 20Gb/s Ground-Referenced Single-Ended Short-Haul Serial Link in 28nm CMOS for Advanced Packaging Applications

John Eyles

ISSCC

2010

The Even/Odd Synchronizer: A Fast, All-Digital Periodic Synchronizer

Stephen Tell

16th International Symposium on Asynchronous Circuits and Systems

2007

A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS

John Poulton

Robert Palmer

Andy Fuller

Trey Greer

John Eyles