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Circuits and VLSI Design
Associated Publications
Simba: Scaling Deep-Learning Inference withMulti-Chip-Module-Based Architecture
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator Designed with a High-Productivity VLSI Methodology
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm
High Performance Graph Convolutional Networks with Applications in Testability Analysis
PRIMAL: Power Inference using Machine Learning
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement
Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference
A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET
Voltage-Follower Coupling Quadrature Oscillator with Embedded Phase-Interpolator in 16nm FinFET
Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model
A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator
RouteNet: routability prediction for mixed-size designs using convolutional neural network
A Modular Digital VLSI Flow for High-Productivity SoC Design
Hardware-Enabled Artificial Intelligence
Ground-Referenced Signaling for Intra-Chip and Short-Reach Chip-to-Chip Interconnects
A Switching Linear Regulator Based on a Fast-Self-Clocked Comparator with Very Low Probability of Meta-stability and a Parallel Analog Ripple Control Module
A 1.17pJ/b 25Gb/s/pin Ground-Referenced Single Ended Serial Link for Off- and On-Package Communication in 16nm CMOS Using a Process- and Temperature-Adaptive Voltage Regulator
Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks
Hybrid Modulation for Near Zero Display Latency
Current parking regulator for zero droop/overshoot load transient response
A 6.5-to-23.3fJ/b/mm Balanced Charge-Recycling Bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with Clock Forwarding and Low-Crosstalk Contraflow Wiring
A 28nm 2Mbit 6T SRAM with Highly Configurable Write Assist Implementation and Capacitor Based Sense Amplifier Input Offset Compen
A Pausible Bisynchronous FIFO for GALS Systems
High-speed Low-power On-chip Global Signaling Design Overview
A Reverse Write Assist Circuit for SRAM Dynamic Write VMIN Tracking using Canary SRAMs
A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications
A 0.54pJ/b 20Gb/s Ground-Referenced Single-Ended Short-Haul Serial Link in 28nm CMOS for Advanced Packaging Applications
A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS
Researchers
Alicia Klinefelter
Ben Boudaoud
Ben Keller
Brian Zimmer
Brucek Khailany
Donghyuk Lee
John Poulton
Josef Spjut
Mark Ren
Matt Fojtik
Matthijs Van keirsbilck
Nathaniel Pinckney
Nikola Nedovic
Priyanka Raina
Rangharajan Venkatesan
Sanquan Song
Sophia Shao
Stephen Tell
Steve Dai
Sudhir Kudva
Tom Gray
Walker Turner
William Dally
Xi Chen
Yanqing Zhang
Yu-Hsin Chen
