Circuits and VLSI Design

Mingjie Liu, Teo Ene, Robert Kirby, Chris Cheng, Nathaniel Pinckney, Rongjian Liang, Jonah Alben, Himyanshu Anand, Sanmitra Banerjee, Ismet Bayraktaroglu, Bonita Bhaskaran, Bryan Catanzaro, Arjun Chaudhuri, Sharon Clay, Bill Dally, Laura Dang, Parikshit Deshpande, Siddhanth Dhodhi, Sameer Halepete, Eric Hill, Jiashang Hu, Sumit Jain, Brucek Khailany, George Kokai, Kishor Kunal, Xiaowei Li, Charley Lind, Hao Liu, Stuart Oberman, Sujeet Omar, Sreedhar Pratty, Jonathan Raman, Ambar Sarkar, Zhengjiang Shao, Hanfei Sun, Pratik P Suthar, Varun Tej, Walker Turner, Kaizhe Xu, Haoxing (Mark) Ren

VerilogEval: Evaluating Large Language Models for Verilog Code Generation

Mingjie Liu, Nathaniel Pinckney, Brucek Khailany, Haoxing (Mark) Ren

2023 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Late Breaking Results: Test Selection For RTL Coverage By Unsupervised Learning From Fast Functional Simulation

Rongjian Liang, Nathaniel Pinckney, Yuji Chai, Haoxing (Mark) Ren, Brucek Khailany

60th Design Automation Conference

Efficient Transformer Inference with Statically Structured Sparse Attention

Steve Dai, Hasan Genc, Rangharajan Venkatesan, Brucek Khailany

2023 60th ACM/IEEE Design Automation Conference (DAC)

Physics-Informed Optical Kernel Regression Using Complex-valued Neural Fields

Guojin Chen, Zehua Pei, Haoyu Yang, Yuzhe Ma, Bei Yu, Martin Wong

60th ACM/IEEE Design Automation Conference

A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS

Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker Turner, Stephen Tell, Nikola Nedovic, John Wilson, William Dally, Tom Gray

2023 IEEE SYMPOSIUM ON VLSI TECHNOLOGY & CIRCUITS

A 9.7fJ/Conv.-Step Capacitive Sensor Readout Circuit with Incremental Zoomed Time Domain Quantization

Zilong Shen, Xiyuan Tang, Zhongyi Wu, Haoyang Luo, Zongnan Wang, Mingjie Liu, Xing Zhang, Yuan Wang

2023 IEEE Custom Integrated Circuits Conference (CICC)

A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS

Yoshinori Nishi, John W. Poulton, Walker Turner, Xi Chen, Sanquan Song, Brian Zimmer, Stephen Tell, Nikola Nedovic, John Wilson, William Dally, Tom Gray

IEEE Journal of Solid-State Circuits ( Volume: 58, Issue: 4, April 2023)

NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model

Chia-Tung (Mark) Ho, Alvin Ho, Matt Fojtik, Minsoo Kim, Shang Wei, Yaguang LI, Brucek Khailany, Haoxing (Mark) Ren

International Symposium on Physical Design 2023

On Legalization of Die Bonding Bumps and Pads for 3D ICs

Sai Pentapati, Anthony Agnesina, Moritz Brunion, Yen-Hsiang Huang, Sung Kyu Lim

International Symposium on Physical Design 2023

Reinforcement Learning Guided Detailed Routing for Custom Circuits

Hao Chen, Kai-Chieh Hsu, Walker Turner, Po-Hsuan Wei, Keren Zhu, David Z. Pan, Haoxing (Mark) Ren

International Symposium on Physical Design 2023

AutoDMP: Automated DREAMPlace-based Macro Placement

Anthony Agnesina, Puranjay Rajvanshi, Tian Yang, Geraldo Pradipta, Austin Jiao, Ben Keller, Brucek Khailany, Haoxing (Mark) Ren

International Symposium on Physical Design 2023

DREAM-GAN: Advancing DREAMPlace towards Commercial-Quality using Generative Adversarial Learning

Yi-Chen Lu, Haoxing (Mark) Ren, Hao-Hsiang Hsiao, Sung Kyu Lim

International Symposium on Physical Design 2023

Enabling Scalable AI Computational Lithography with Physics-Inspired Models

Haoyu Yang, Haoxing (Mark) Ren

2023 28th Asia and South Pacific Design Automation Conference (ASP-DAC)

Beyond CPO: A Motivation and Approach for Bringing Optics onto the Silicon Interposer

Ben Lee, Nikola Nedovic, Trey Greer, Tom Gray

Journal of Lightwave Technology

A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm

Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen Tell, Brian Zimmer, Charbel Sakr, William Dally, Tom Gray, Brucek Khailany

Journal of Solid-State Circuits

BufFormer: A Generative ML Framework for Scalable Buffering

Rongjian Liang, Siddhartha Nath, Anand Rajaram, Jiang Hu, Haoxing (Mark) Ren

28th Asia and South Pacific Design Automation Conference

2022

Efficient Arithmetic Block Identification with Graph Learning and Network-flow

Ziyi Wang, Zhuolun He, Chen Bai, Haoyu Yang, Bei Yu

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design

Mingjie Liu, Haoyu Yang, Zongyi Li, Kumara Sastry, Saumyadip Mukhopadhyay, Selim Dogru, Anima Anandkumar, David Z. Pan, Brucek Khailany, Haoxing (Mark) Ren

Workshop on ML for Systems at NeurIPS

LNS-Madam: Low-Precision Training in Logarithmic Number System Using Multiplicative Weight Update

Jiawei Zhao, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, Mustafa Ali, Ming-Yu Liu, Brucek Khailany, William Dally, Anima Anandkumar

IEEE Transactions on Computers (Volume: 71, Issue: 12, 01 December 2022)

TransSizer: A Novel Transformer-Based Fast Gate Sizer

Siddhartha Nath, Geraldo Pradipta, Corey Hu, Tian Yang, Brucek Khailany, Haoxing (Mark) Ren

2022 International Conference on Computer-Aided Design

TAG: Learning Circuit Spatial Embedding from Layouts

Keren Zhu, Hao Chen, Walker Turner, George F. Kokai, Po-Hsuan Wei, David Z. Pan, Haoxing (Mark) Ren

2022 International Conference on Computer-Aided Design

Why are Graph Neural Networks Effective for EDA Problems?

Haoxing (Mark) Ren, Siddhartha Nath, Yanqing Zhang, Hao Chen, Mingjie Liu

2022 International Conference on Computer-Aided Design

Photonic Circuits for Accelerated Computing Systems

Ben Lee

European Conference on Optical Communication (ECOC), 2022

Placement Optimization via PPA-Directed Graph Clustering

Yi-Chen Lu, Tian Yang, Sung Kyu Lim, Haoxing (Mark) Ren

MLCAD '22: Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD

XT-PRAGGMA: Crosstalk Pessimism Reduction Accessible by GPU Gate-level Simulations and Machine Learning

Vidya Chhabria, Ben Keller, Yanqing Zhang, Sandeep Vollala, Sreedhar Patty, Haoxing (Mark) Ren, Brucek Khailany

MLCAD '22: Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD

From RTL to CUDA: A GPU Acceleration Flow for RTL Simulation with Batch Stimulus

Dian-Lun Lin, Haoxing (Mark) Ren, Yanqing Zhang, Brucek Khailany, Tsung-Wei Huang

51st International Conference on Parallel Processing (ICPP '22)

A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS

Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker Turner, Stephen Tell, Nikola Nedovic, John Wilson, William Dally, Tom Gray

2022 IEEE SYMPOSIUM ON VLSI TECHNOLOGY & CIRCUITS

A 17–95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm

Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen Tell, Brian Zimmer, William Dally, Tom Gray, Brucek Khailany

2022 Symposium on VLSI Technology & Circuits Digest of Technical Papers

Saving PAM4 Bus Energy with SMOREs: Sparse Multi-level Opportunistic Restricted Encodings

Mike O'Connor, Donghyuk Lee, Niladrish Chatterjee, Michael B. Sullivan, Steve Keckler

International Symposium on High-Performance Computer Architecture (HPCA)

AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies

Hao Chen, Walker Turner, Sanquan Song, Keren Zhu, George Kokai, Brian Zimmer, Tom Gray, Brucek Khailany, Haoxing (Mark) Ren

International Symposium on Physical Design 2022

Routability-Aware Placement for Advanced FinFET Analog Circuits with Satisfiability Modulo Theories

Hao Chen, Walker Turner, David Z. Pan, Haoxing (Mark) Ren

Design, Automation & Test in Europe 2022

Generic Lithography Modeling with Dual-band Optics-Inspired Neural Networks

Haoyu Yang, Zongyi Li, Kumara Sastry, Saumyadip Mukhopadhyay, Mark Kilgard, Anima Anandkumar, Brucek Khailany, Vivek Singh, Haoxing (Mark) Ren

2022 Design Automation Conference

GATSPI: GPU Accelerated Gate-Level Simulation for Power Improvement

Yanqing Zhang, Haoxing (Mark) Ren, Akshay Sridharan, Brucek Khailany

2022 Design Automation Conference

Driving Down Link Energy and Driving Up Link Density in GPU Networks

Ben Lee

Optical Fiber Communications (OFC) Conference, 2022

DeePattern: Layout Pattern Generation with Transforming Convolutional Auto-Encoder

Haoyu Yang, Shuhe Li, Wen Chen, Piyush Pathak, Frank Gennari, Ya-Chieh Lai, Bei Yu

IEEE Transactions on Semiconductor Manufacturing

Best Paper Award

Machine Learning and Algorithms: Let Us Team Up for EDA

Haoxing (Mark) Ren, Brucek Khailany, Matt Fojtik, Yanqing Zhang

IEEE Design & Test

2021

NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning

Haoxing (Mark) Ren, Matt Fojtik, Brucek Khailany

Design Automation Conference (DAC) 2021 (Invited special session paper)

Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers

Jacob R. Stevens, Rangharajan Venkatesan, Steve Dai, Brucek Khailany, Anand Raghunathan

Design Automation Conference (DAC) 2021

IPA: Floorplan-Aware SystemC Interconnect Performance Modeling and Generation for HLS-based SoCs

Nathaniel Pinckney, Rangharajan Venkatesan, Ben Keller, Brucek Khailany

IEEE/ACM International Conference on Computer-Aided Design (ICCAD ’21)

Graph Learning-Based Arithmetic Block Identification

Zhuolun He, Ziyi Wang, Chen Bai, Haoyu Yang, Bei Yu

IEEE/ACM International Conference on Computer-Aided Design

Simba: scaling deep-learning inference with chiplet-based architecture

Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Brucek Khailany, Steve Keckler

Communications of the ACM

ACM Research Highlight

VS-QUANT: Per-Vector Scaled Quantization for Accurate Low-Precision Neural Network Inference

Steve Dai, Rangharajan Venkatesan, Haoxing (Mark) Ren, Brian Zimmer, William Dally, Brucek Khailany

MLSys 2021

Fair and Comprehensive Benchmarking of Machine Learning Processing Chips

Geoffrey W. Burr, SukHwan Lim, Boris Murmann, Rangharajan Venkatesan, Marian Verhelst

https://ieeexplore.ieee.org/document/9367229

Verifying High-Level Latency-Insensitive Designs with Formal Model Checking

Steve Dai, Alicia Klinefelter, Haoxing (Mark) Ren, Rangharajan Venkatesan, Ben Keller, Nathaniel Pinckney, Brucek Khailany

arXiv

Ground-Referenced Single-Ended Signaling: Applications for High-Density Short-Haul Communication Systems

John Wilson, Walker Turner, John Poulton

Solid-State Circuits Magazine

MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification

Vidya A. Chhabria, Yanqing Zhang, Haoxing (Mark) Ren, Ben Keller, Brucek Khailany, Sachin S. Sapatnekar

2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)

Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization

Mingjie Liu, Walker Turner, George Kokai, David Z. Pan, Brucek Khailany, Haoxing (Mark) Ren

2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)

Standard Cell Routing with Reinforcement Learning and Genetic Algorithm in Advanced Technology Nodes

Haoxing (Mark) Ren, Matt Fojtik

26th Asia and South Pacific Design Automation Conference (ASP-DAC) 2021

2020

NVCell: Generate Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning

Haoxing (Mark) Ren, Matt Fojtik, Brucek Khailany

Workshop on ML for Systems at NeurIPS

How Software Can "Chip In" to the IC Design Process: A Multidisciplinary Approach May Attract New Talent and Accelerate Innovation

Alicia Klinefelter

IEEE Solid-State Circuits Magazine

Opportunities for RTL and Gate Level Simulation using GPUs

Yanqing Zhang, Haoxing (Mark) Ren, Brucek Khailany

IEEE/ACM International Conference on Computer-Aided Design (ICCAD ’20)

Accelerating Chip Design with Machine Learning

Brucek Khailany, Haoxing (Mark) Ren, Steve Dai, Saad Godil, Ben Keller, Robert Kirby, Alicia Klinefelter, Rangharajan Venkatesan, Yanqing Zhang, Bryan Catanzaro, William Dally

IEEE Micro

ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks

Haoxing (Mark) Ren, George Kokai, Walker Turner, Ting-Sheng Ku

Design Automation Conference (DAC) 2020

GRANNITE: Graph Neural Network Inference for Transferable Power Estimation

Yanqing Zhang, Haoxing (Mark) Ren, Brucek Khailany

Design Automation Conference (DAC) 2020

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement

Yibo Lin, Zixuan Jiang, Jiaqi Gu, Wuxi Li, Shounak Dhar, Haoxing (Mark) Ren, Brucek Khailany, David Z. Pan

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (…

2021 IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award

Reference-Noise Compensation Scheme for Single- Ended Package-to-Package Links

Xi Chen, Nikola Nedovic, Stephen Tell, Sudhir Kudva, Brian Zimmer, Trey Greer, John Poulton, Sanquan Song, Walker Turner, John Wilson, Tom Gray

2020 International Solid-State Circuits Conference

ABCDPlace: Accelerated Batch-based Concurrent Detailed Placement on Multi-threaded CPUs and GPUs

Yibo Lin, Wuxi Li, Jiaqi Gu, Haoxing (Mark) Ren, Brucek Khailany, David Z. Pan

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (…

A 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm

Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Steve Keckler, Brucek Khailany

IEEE Journal of Solid-State Circuits (JSSC)

JSSC 2020 Best Paper award

FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning

Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Haoxing (Mark) Ren, Yanqing Zhang, Brucek Khailany, Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza

ASP-DAC 2020

PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network

Zhiyao Xie, Haoxing (Mark) Ren, Brucek Khailany, Ye Sheng, Santosh Santosh, Jiang Hu, Yiran Chen

ASP-DAC 2020

2019

MAGNet: A Modular Accelerator Generator for Neural Networks

Rangharajan Venkatesan, Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matt Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Yanqing Zhang, Brian Zimmer, William Dally, Joel Emer, Steve Keckler, Brucek Khailany

International Conference On Computer Aided Design (ICCAD)

Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture

Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Brucek Khailany, Steve Keckler

International Symposium on Microarchitecture (MICRO)

Best Paper award, IEEE Micro Top Picks in Computer Architecture (Honorable Mention)

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator Designed with a High-Productivity VLSI Methodology

Rangharajan Venkatesan, Sophia Shao, Brian Zimmer, Jason Clemons, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Steve Keckler, Brucek Khailany

Hot Chips: A Symposium on High Performance Chips

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm

Brian Zimmer, Rangharajan Venkatesan, Sophia Shao, Jason Clemons, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Steve Keckler, Brucek Khailany

Symposium on VLSI Circuits

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement

Yibo Lin, Shounak Dhar, Wuxi Li, Haoxing (Mark) Ren, Brucek Khailany, David Z. Pan

Design Automation Conference (DAC) 2019

DAC 2019 Best Paper Award

PRIMAL: Power Inference using Machine Learning

Yuan Zhou, Haoxing (Mark) Ren, Yanqing Zhang, Ben Keller, Brucek Khailany, Zhiru Zhang

Design Automation Conference (DAC)

High Performance Graph Convolutional Networks with Applications in Testability Analysis

Yuzhe Ma, Haoxing (Mark) Ren, Brucek Khailany, Harbinder Sikka, Lijuan Luo, Karthikeyan Natarajan, Bei Yu

Design Automation Conference (DAC)

Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference

Angad S. Rekhi, Brian Zimmer, Nikola Nedovic, Nigxi Liu, Rangharajan Venkatesan, Miaorong Wang, Brucek Khailany, William Dally, Tom Gray

Design Automation Conference (DAC)

A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET

Matt Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Stephen Tell, Brian Zimmer, Tezaswi Raja, Kevin Zhou, William Dally, Brucek Khailany

ASYNC 2019

ASYNC 2019 Best Paper Award

Voltage-Follower Coupling Quadrature Oscillator with Embedded Phase-Interpolator in 16nm FinFET

Xi Chen, Sanquan Song, John Poulton, Nikola Nedovic, Brian Zimmer, Stephen Tell, Tom Gray

IEEE Custom Integrated Circuits Conference 2019

Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model

Yu-Hung Huang, Zhiyao Xie, Guan-Qi Fang, Tao-Chun Yu, Haoxing (Mark) Ren, Shao-Yun Fang, Yiran Chen, Jiang Hu

Design, Automation and Test in Europe

A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator

John Poulton, John Wilson, Walker Turner, Brian Zimmer, Xi Chen, Sudhir Kudva, Sanquan Song, Stephen Tell, Nikola Nedovic, Wenxu Zhao, Sunil Sudhakaran, Tom Gray, William Dally

IEEE JOURNAL OF SOLID-STATE CIRCUITS

2018

RouteNet: Routability Prediction for Mixed-size Designs using Convolutional Neural Network

Zhiyao Xie, Yu-Hung Huang, Guan-Qi Fang, Haoxing (Mark) Ren, Shao-Yun Fang, Yiran Chen, Hu Jiang

International Conference On Computer Aided Design

A Modular Digital VLSI Flow for High-Productivity SoC Design

Brucek Khailany, Evgeni Krimer, Rangharajan Venkatesan, Jason Clemons, Joel Emer, Matt Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Pinckney, Sophia Shao, Shreesha Srinath, Christopher Torng, Sam (Likun) Xi, Yanqing Zhang, Brian Zimmer

Design Automation Conference (DAC)

Hardware-Enabled Artificial Intelligence

William Dally, Tom Gray, John Poulton, Brucek Khailany, John Wilson, Larry Dennison

Symposia on VLSI Technology and Circuits

Ground-Referenced Signaling for Intra-Chip and Short-Reach Chip-to-Chip Interconnects

Walker Turner, John Poulton, John Wilson, Xi Chen, Stephen Tell, Matt Fojtik, Trey Greer, Brian Zimmer, Sanquan Song, Nikola Nedovic, Sudhir Kudva, Sunil Sudhakaran, Rizwan Bashirullah, Wenxu Zhao, William Dally, Tom Gray

Custom Integrated Circuits Conference

A Switching Linear Regulator Based on a Fast-Self-Clocked Comparator with Very Low Probability of Meta-stability and a Parallel Analog Ripple Control Module

Sudhir Kudva, Sanquan Song, John Poulton, John Wilson, Wenxu Zhao, Tom Gray

Custom Integrated Circuits Conference

A 1.17pJ/b 25Gb/s/pin Ground-Referenced Single Ended Serial Link for Off- and On-Package Communication in 16nm CMOS Using a Process- and Temperature-Adaptive Voltage Regulator

John Wilson, Walker Turner, John Poulton, Brian Zimmer, Xi Chen, Sanquan Song, Stephen Tell, Nikola Nedovic, Wenxu Zhao, Sunil Sudhakaran, Tom Gray, William Dally

ISSCC

2017

Xylem: Enhancing Vertical Thermal Conduction in 3D Processor-Memory Stacks

Aditya Agrawal, Josep Torrellas, Sachin Idgunji

International Symposium on Microarchitecture (MICRO)

Detecting and Mitigating Data-Dependent DRAM Failures by Exploiting Current Memory Content

Samira Khan, Chris Wilkerson, Zhe Wang, Alaa R. Alameldeen, Donghyuk Lee, Onur Mutlu

International Symposium on Microarchitecture (MICRO)

Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology

Vivek Seshadri, Donghyuk Lee, Thomas Mullins, Hasan Hassan, Amirali Boroumand, Jeremie Kim, Michael A. Kozuch, Onur Mutlu, Phillip B. Gibbons, Todd C. Mowry

International Symposium on Microarchitecture (MICRO)

2016

Snatch: Opportunistically Reassigning Power Allocation between Processor and Memory in 3D Stacks

Dimitrios Skarlatos, Renji Thomas, Aditya Agrawal, Shibin Qin, Robert Pilawa-Podgurski, Ulya R. Karpuzcu, Radu Teodorescu, Nam Sung Kim, Josep Torrellas

International Symposium on Microarchitecture (MICRO)

Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks

Divya Akella Kamakshi, Matt Fojtik, Brucek Khailany, Sudhir Kudva, Yaping Zhou, Benton H. Calhoun

ASYNC 2016

ASYNC 2016 Best Paper Award Nominee

Hybrid Modulation for Near Zero Display Latency

Trey Greer, Josef Spjut, David Luebke, Turner Whitted

Current parking regulator for zero droop/overshoot load transient response

Sudhir Kudva, William Dally, Trey Greer, Tom Gray

Applied Power Electronics Conference and Exposition (APEC)

A 6.5-to-23.3fJ/b/mm Balanced Charge-Recycling Bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with Clock Forwarding and Low-Crosstalk Contraflow Wiring

John Wilson, Matt Fojtik, John Poulton, Xi Chen, Stephen Tell, Trey Greer, Tom Gray, William Dally