Research Areas

Circuits and VLSI Design

Associated Publications

2022

Saving PAM4 Bus Energy with SMOREs: Sparse Multi-level Opportunistic Restricted Encodings
Mike O'Connor, Donghyuk Lee, Niladrish Chatterjee, Mike Sullivan, Steve Keckler
IEEE International Symposium on High-Performance Computer Architecture (HPCA)
Generic Lithography Modeling with Dual-band Optics-Inspired Neural Networks
Haoyu Yang, Zongyi Li, Kumara Sastry, Saumyadip Mukhopadhyay, Mark Kilgard, Anima Anandkumar, Brucek Khailany, Vivek Singh, Mark Ren
2022 Design Automation Conference
GATSPI: GPU Accelerated Gate-Level Simulation for Power Improvement
Yanqing Zhang, Mark Ren, Akshay Sridharan, Brucek Khailany
2022 Design Automation Conference
Driving Down Link Energy and Driving Up Link Density in GPU Networks
Ben Lee
Optical Fiber Communications (OFC) Conference, 2022

2021

Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers
Jacob R. Stevens, Rangharajan Venkatesan, Steve Dai, Brucek Khailany, Anand Raghunathan
Design Automation Conference (DAC) 2021
NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning
Mark Ren, Matt Fojtik, Brucek Khailany
Design Automation Conference (DAC) 2021 (Invited special session paper)
IPA: Floorplan-Aware SystemC Interconnect Performance Modeling and Generation for HLS-based SoCs
Nathaniel Pinckney, Rangharajan Venkatesan, Ben Keller, Brucek Khailany
IEEE/ACM International Conference on Computer-Aided Design (ICCAD ’21)
Graph Learning-Based Arithmetic Block Identification
Zhuolun He, Ziyi Wang, Chen Bai, Haoyu Yang, Bei Yu
IEEE/ACM International Conference on Computer-Aided Design
Simba: scaling deep-learning inference with chiplet-based architecture
Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Brucek Khailany, Steve Keckler
Communications of the ACM
VS-QUANT: Per-Vector Scaled Quantization for Accurate Low-Precision Neural Network Inference
Steve Dai, Rangharajan Venkatesan, Mark Ren, Brian Zimmer, William Dally, Brucek Khailany
MLSys 2021
Verifying High-Level Latency-Insensitive Designs with Formal Model Checking
Steve Dai, Alicia Klinefelter, Mark Ren, Rangharajan Venkatesan, Ben Keller, Nathaniel Pinckney, Brucek Khailany
arXiv
Ground-Referenced Single-Ended Signaling: Applications for High-Density Short-Haul Communication Systems
John Wilson, Walker Turner, John Poulton
Solid-State Circuits Magazine
MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification
Vidya A. Chhabria, Yanqing Zhang, Mark Ren, Ben Keller, Brucek Khailany, Sachin S. Sapatnekar
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization
Mingjie Liu, Walker Turner, George Kokai, David Z. Pan, Brucek Khailany, Mark Ren
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Standard Cell Routing with Reinforcement Learning and Genetic Algorithm in Advanced Technology Nodes
Mark Ren, Matt Fojtik
26th Asia and South Pacific Design Automation Conference (ASP-DAC) 2021

2020

NVCell: Generate Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning
Mark Ren, Matt Fojtik, Brucek Khailany
Workshop on ML for Systems at NeurIPS
How Software Can "Chip In" to the IC Design Process: A Multidisciplinary Approach May Attract New Talent and Accelerate Innovation
Alicia Klinefelter
IEEE Solid-State Circuits Magazine
Opportunities for RTL and Gate Level Simulation using GPUs
Yanqing Zhang, Mark Ren, Brucek Khailany
IEEE/ACM International Conference on Computer-Aided Design (ICCAD ’20)
Accelerating Chip Design with Machine Learning
Brucek Khailany, Mark Ren, Steve Dai, Saad Godil, Ben Keller, Robert Kirby, Alicia Klinefelter, Rangharajan Venkatesan, Yanqing Zhang, Bryan Catanzaro, William Dally
IEEE Micro
ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks
Mark Ren, George Kokai, Walker Turner, Ting-Sheng Ku
Design Automation Conference (DAC) 2020
GRANNITE: Graph Neural Network Inference for Transferable Power Estimation
Yanqing Zhang, Mark Ren, Brucek Khailany
Design Automation Conference (DAC) 2020
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement
Yibo Lin, Zixuan Jiang, Jiaqi Gu, Wuxi Li, Shounak Dhar, Mark Ren, Brucek Khailany, David Z. Pan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (…
2021 IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award
Reference-Noise Compensation Scheme for Single- Ended Package-to-Package Links
Xi Chen, Nikola Nedovic, Stephen Tell, Sudhir Kudva, Brian Zimmer, Trey Greer, John Poulton, Sanquan Song, Walker Turner, John Wilson, Tom Gray
2020 International Solid-State Circuits Conference
ABCDPlace: Accelerated Batch-based Concurrent Detailed Placement on Multi-threaded CPUs and GPUs
Yibo Lin, Wuxi Li, Jiaqi Gu, Mark Ren, Brucek Khailany, David Z. Pan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (…
A 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm
Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Steve Keckler, Brucek Khailany
IEEE Journal of Solid-State Circuits (JSSC)
JSSC 2020 Best Paper Award
FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning
Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Mark Ren, Yanqing Zhang, Brucek Khailany, Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza
ASP-DAC 2020
PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network
Zhiyao Xie, Mark Ren, Brucek Khailany, Ye Sheng, Santosh Santosh, Jiang Hu, Yiran Chen
ASP-DAC 2020

2019

MAGNet: A Modular Accelerator Generator for Neural Networks
Rangharajan Venkatesan, Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matt Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Yanqing Zhang, Brian Zimmer, William Dally, Joel Emer, Steve Keckler, Brucek Khailany
International Conference On Computer Aided Design
Simba: Scaling Deep-Learning Inference withMulti-Chip-Module-Based Architecture
Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Brucek Khailany, Steve Keckler
52nd IEEE/ACM International Symposium on Microarchitecture
MICRO52 Best Paper Award
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator Designed with a High-Productivity VLSI Methodology
Rangharajan Venkatesan, Sophia Shao, Brian Zimmer, Jason Clemons, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Steve Keckler, Brucek Khailany
Hot Chips: A Symposium on High Performance Chips
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm
Brian Zimmer, Rangharajan Venkatesan, Sophia Shao, Jason Clemons, Matt Fojtik, Ted Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen Tell, Yanqing Zhang, William Dally, Joel Emer, Tom Gray, Steve Keckler, Brucek Khailany
Symposium on VLSI Circuits Digest of Technical Papers
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement
Yibo Lin, Shounak Dhar, Wuxi Li, Mark Ren, Brucek Khailany, David Z. Pan
Design Automation Conference (DAC) 2019
DAC 2019 Best Paper Award
High Performance Graph Convolutional Networks with Applications in Testability Analysis
Yuzhe Ma, Mark Ren, Brucek Khailany, Harbinder Sikka, Lijuan Luo, Karthikeyan Natarajan, Bei Yu
Design Automation Conference (DAC)
Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference
Angad S. Rekhi, Brian Zimmer, Nikola Nedovic, Nigxi Liu, Rangharajan Venkatesan, Miaorong Wang, Brucek Khailany, William Dally, Tom Gray
Design Automation Conference (DAC)
PRIMAL: Power Inference using Machine Learning
Yuan Zhou, Mark Ren, Yanqing Zhang, Ben Keller, Brucek Khailany, Zhiru Zhang
Design Automation Conference (DAC)
A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET
Matt Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Stephen Tell, Brian Zimmer, Tezaswi Raja, Kevin Zhou, William Dally, Brucek Khailany
ASYNC 2019
ASYNC 2019 Best Paper Award
Voltage-Follower Coupling Quadrature Oscillator with Embedded Phase-Interpolator in 16nm FinFET
Xi Chen, Sanquan Song, John Poulton, Nikola Nedovic, Brian Zimmer, Stephen Tell, Tom Gray
IEEE Custom Integrated Circuits Conference 2019
Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model
Yu-Hung Huang, Zhiyao Xie, Guan-Qi Fang, Tao-Chun Yu, Mark Ren, Shao-Yun Fang, Yiran Chen, Jiang Hu
Design, Automation and Test in Europe
A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator
John Poulton, John Wilson, Walker Turner, Brian Zimmer, Xi Chen, Sudhir Kudva, Sanquan Song, Stephen Tell, Nikola Nedovic, Wenxu Zhao, Sunil Sudhakaran, Tom Gray, William Dally
IEEE JOURNAL OF SOLID-STATE CIRCUITS

2018

RouteNet: Routability Prediction for Mixed-size Designs using Convolutional Neural Network
Zhiyao Xie, Yu-Hung Huang, Guan-Qi Fang, Mark Ren, Shao-Yun Fang, Yiran Chen, Hu Jiang
International Conference On Computer Aided Design
A Modular Digital VLSI Flow for High-Productivity SoC Design
Brucek Khailany, Evgeni Krimer, Rangharajan Venkatesan, Jason Clemons, Joel Emer, Matt Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Pinckney, Sophia Shao, Shreesha Srinath, Christopher Torng, Sam (Likun) Xi, Yanqing Zhang, Brian Zimmer
Design Automation Conference (DAC)
Hardware-Enabled Artificial Intelligence
William Dally, Tom Gray, John Poulton, Brucek Khailany, John Wilson, Larry Dennison
Symposia on VLSI Technology and Circuits
Ground-Referenced Signaling for Intra-Chip and Short-Reach Chip-to-Chip Interconnects
Walker Turner, John Poulton, John Wilson, Xi Chen, Stephen Tell, Matt Fojtik, Trey Greer, Brian Zimmer, Sanquan Song, Nikola Nedovic, Sudhir Kudva, Sunil Sudhakaran, Rizwan Bashirullah, Wenxu Zhao, William Dally, Tom Gray
Custom Integrated Circuits Conference
A Switching Linear Regulator Based on a Fast-Self-Clocked Comparator with Very Low Probability of Meta-stability and a Parallel Analog Ripple Control Module
Sudhir Kudva, Sanquan Song, John Poulton, John Wilson, Wenxu Zhao, Tom Gray
Custom Integrated Circuits Conference
A 1.17pJ/b 25Gb/s/pin Ground-Referenced Single Ended Serial Link for Off- and On-Package Communication in 16nm CMOS Using a Process- and Temperature-Adaptive Voltage Regulator
John Wilson, Walker Turner, John Poulton, Brian Zimmer, Xi Chen, Sanquan Song, Stephen Tell, Nikola Nedovic, Wenxu Zhao, Sunil Sudhakaran, Tom Gray, William Dally
ISSCC

2016

Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks
Divya Akella Kamakshi, Matt Fojtik, Brucek Khailany, Sudhir Kudva, Yaping Zhou, Benton H. Calhoun
ASYNC 2016
ASYNC 2016 Best Paper Award Nominee
Hybrid Modulation for Near Zero Display Latency
Trey Greer, Josef Spjut, David Luebke, Turner Whitted
Current parking regulator for zero droop/overshoot load transient response
Sudhir Kudva, William Dally, Trey Greer, Tom Gray
Applied Power Electronics Conference and Exposition (APEC)
A 6.5-to-23.3fJ/b/mm Balanced Charge-Recycling Bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with Clock Forwarding and Low-Crosstalk Contraflow Wiring
John Wilson, Matt Fojtik, John Poulton, Xi Chen, Stephen Tell, Trey Greer, Tom Gray, William Dally
International Solid-State Circuits Conference (ISSCC 2016)
A 28nm 2Mbit 6T SRAM with Highly Configurable Write Assist Implementation and Capacitor Based Sense Amplifier Input Offset Compen
Mahmut Sinangil, John Poulton, Matt Fojtik, Trey Greer, Stephen Tell, Andy Gotterba, Jesse Wang, Jason Golbus, William Dally, Tom Gray
Journal of Solid State Circuits

2015

A Pausible Bisynchronous FIFO for GALS Systems
Ben Keller, Matt Fojtik, Brucek Khailany
ASYNC 2015
High-speed Low-power On-chip Global Signaling Design Overview
Xi Chen, John Wilson, John Poulton, Rizwan Bashirullah, Tom Gray
DesignCon

2014

A Reverse Write Assist Circuit for SRAM Dynamic Write VMIN Tracking using Canary SRAMs
Arijit Banerjee, Mahmut Sinangil, John Poulton, Tom Gray, Ben Calhoun
International Symposium on Quality Electronic Design

2013

A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications
John Poulton, William Dally, Xi Chen, John Eyles, Trey Greer, Stephen Tell, John Wilson, Tom Gray
Journal of Solid State Circuits
A 0.54pJ/b 20Gb/s Ground-Referenced Single-Ended Short-Haul Serial Link in 28nm CMOS for Advanced Packaging Applications
John Poulton, William Dally, Xi Chen, John Eyles, Trey Greer, Stephen Tell, Tom Gray
ISSCC

2010

The Even/Odd Synchronizer: A Fast, All-Digital Periodic Synchronizer
William Dally, Stephen Tell
16th International Symposium on Asynchronous Circuits and Systems

2007

A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS
John Poulton, Robert Palmer, Andy Fuller, Trey Greer, John Eyles, William Dally, Mark Horowitz
IEEE Journal of Solid-State Circuits

Researchers

Anthony Agnesina
Ben Lee
Brian Zimmer
Charbel Sakr
Donghyuk Lee
Georgios Kalogerakis
Haoyu Yang
John Wilson
Josef Spjut
Li Xu
Mahmut Ersin Sinangil
Mark Ren
Matt Fojtik
Matthijs Van keirsbilck
Muya Chang
Nicolai Oswald
Nikola Nedovic
Qijing Jenny Huang
Rangharajan Venkatesan
Rongjian Liang
Sanquan Song
Siddhartha Nath
Stephen Tell
Tom Gray
William Dally
Xi Chen
Yanqing Zhang
Yoshi Nishi