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Research Areas
Circuits and VLSI Design
Associated Publications
Accelerating Chip Design with Machine LearningParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks
GRANNITE: Graph Neural Network Inference for Transferable Power Estimation
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement
Reference-Noise Compensation Scheme for Single- Ended Package-to-Package Links
ABCDPlace: Accelerated Batch-based Concurrent Detailed Placement on Multi-threaded CPUs and GPUs
A 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm
FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning
PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network
MAGNet: A Modular Accelerator Generator for Neural Networks
Simba: Scaling Deep-Learning Inference withMulti-Chip-Module-Based Architecture
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator Designed with a High-Productivity VLSI Methodology
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement
High Performance Graph Convolutional Networks with Applications in Testability Analysis
Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference
PRIMAL: Power Inference using Machine Learning
A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET
Voltage-Follower Coupling Quadrature Oscillator with Embedded Phase-Interpolator in 16nm FinFET
Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model
A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator
RouteNet: routability prediction for mixed-size designs using convolutional neural network
A Modular Digital VLSI Flow for High-Productivity SoC Design
Hardware-Enabled Artificial Intelligence
Ground-Referenced Signaling for Intra-Chip and Short-Reach Chip-to-Chip Interconnects
A Switching Linear Regulator Based on a Fast-Self-Clocked Comparator with Very Low Probability of Meta-stability and a Parallel Analog Ripple Control Module
A 1.17pJ/b 25Gb/s/pin Ground-Referenced Single Ended Serial Link for Off- and On-Package Communication in 16nm CMOS Using a Process- and Temperature-Adaptive Voltage Regulator
Hybrid Modulation for Near Zero Display Latency
Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks
Current parking regulator for zero droop/overshoot load transient response
A 28nm 2Mbit 6T SRAM with Highly Configurable Write Assist Implementation and Capacitor Based Sense Amplifier Input Offset Compen
A 6.5-to-23.3fJ/b/mm Balanced Charge-Recycling Bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with Clock Forwarding and Low-Crosstalk Contraflow Wiring
A Pausible Bisynchronous FIFO for GALS Systems
High-speed Low-power On-chip Global Signaling Design Overview
A Reverse Write Assist Circuit for SRAM Dynamic Write VMIN Tracking using Canary SRAMs
A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications
A 0.54pJ/b 20Gb/s Ground-Referenced Single-Ended Short-Haul Serial Link in 28nm CMOS for Advanced Packaging Applications
The Even/Odd Synchronizer: A Fast, All-Digital Periodic Synchronizer
A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS
Researchers
Alicia KlinefelterBen Boudaoud
Ben Keller
Brian Zimmer
Brucek Khailany
Donghyuk Lee
John Poulton
Josef Spjut
Mark Ren
Matt Fojtik
Matthijs Van keirsbilck
Nandish Mehta
Nathaniel Pinckney
Nikola Nedovic
Priyanka Raina
Rangharajan Venkatesan
Sanquan Song
Stephen Tell
Steve Dai
Sudhir Kudva
Tom Gray
Walker Turner
William Dally
Xi Chen
Yanqing Zhang
Yoshi Nishi