Beyond CPO: A Motivation and Approach for Bringing Optics onto the Silicon Interposer

Co-packaged optics (CPO) technology is well positioned to break through the bottlenecks that impede efficient bandwidth scaling in key near-term commercial integrated circuits. In this paper, we begin by providing some historical context for this important sea change in the optical communications industry. Then, motivated by GPU-based accelerated computing requirements, we investigate the next pain points that are poised to constrain bandwidth and efficiency in future CPO-based systems. We identify 2.5D integrated optics (i.e., bringing optics onto the interposer) as a promising solution that can enable continued scaling for these systems due to the dense wiring available which facilitates more efficient slow-and-wide electrical interfaces. We explore the benefits, challenges, and requirements associated with such tight coupling of the processors and optical engines by considering high-level photonic link design, technology, and packaging. We demonstrate the viability of a control loop which can adequately regulate temperature within the aggressive thermal environment. Then, we introduce a custom simulation framework that allows quantified comparisons of detailed design decisions; the simulations validate the feasibility of the general approach while also providing key guidance to designers on best directions to pursue for efficient optimization.