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People

 

Trey Greer

Trey Greer joined NVIDIA's Circuits Research Group in April 2009. Prior to joining NVIDIA, he has worked on a variety of high-performance interconnect and graphics projects at Rambus, Velio Communications, PixelFusion, and Hewlett-Packard.

Main Field of Interest: 
Circuits and VLSI Design

Publications

Reference-Noise Compensation Scheme for Single- Ended Package-to-Package Links
Toward Standardized Classification of Foveated Displays
Foveated AR: Dynamically-Foveated Augmented Reality Display
Matching Prescription & Visual Acuity: Towards AR for Humans
Ground-Referenced Signaling for Intra-Chip and Short-Reach Chip-to-Chip Interconnects
Hybrid Modulation for Near Zero Display Latency
Current parking regulator for zero droop/overshoot load transient response
A 6.5-to-23.3fJ/b/mm Balanced Charge-Recycling Bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with Clock Forwarding and Low-Crosstalk Contraflow Wiring
A 28nm 2Mbit 6T SRAM with Highly Configurable Write Assist Implementation and Capacitor Based Sense Amplifier Input Offset Compen
A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications
A 0.54pJ/b 20Gb/s Ground-Referenced Single-Ended Short-Haul Serial Link in 28nm CMOS for Advanced Packaging Applications
A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS
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