Publications

Differentiable Tier Assignment for Timing and Congestion-Aware Routing in 3D ICs

2026 ACM/IEEE 31st Asia South Pacific Design Automation Conference (ASP-DAC)

Differentiable Tier Assignment for Timing and Congestion-Aware Routing in 3D ICs

Code, Not Canvas: Multi-Agent Layout Generation Beyond Vision Models

2026 31st ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC)

C3PO: Commercial-Quality Global Placement via Coherent, Concurrent Timing, Routability, and Wirelength Optimization

2026 ACM/IEEE 31st Asia South Pacific Design Automation Conference (ASP-DAC)

preprint
C3PO: Commercial-Quality Global Placement via Coherent, Concurrent Timing, Routability, and Wirelength Optimization

LLM-Enhanced GPU-Optimized Physical Design at Scale (invited)

2025 ACM/IEEE International Conference on Computer-Aided Design (ICCAD)

preprint

BUFFALO: PPA-Configurable, LLM-based Buffer Tree Generation via Group Relative Policy Optimization

2025 ACM/IEEE International Conference on Computer-Aided Design (ICCAD)

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BUFFALO: PPA-Configurable, LLM-based Buffer Tree Generation via Group Relative Policy Optimization

2025 ICCAD CAD Contest Problem C: Incremental Placement Optimization Beyond Detailed Placement: Simultaneous Gate Sizing, Buffering, and Cell Relocation

2025 ACM/IEEE International Conference on Computer-Aided Design (ICCAD)

preprint

ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generation

2025 ACM/IEEE Symposium on Machine Learning for CAD (MLCAD)

Netlistify: Transforming Circuit Schematics into Netlists with Deep Learning

2025 ACM/IEEE Symposium on Machine Learning for CAD (MLCAD)
Best Artifact Award

preprint

ASPEN: LLM-Guided E-Graph Rewriting for RTL Datapath Optimization

2025 ACM/IEEE Symposium on Machine Learning for CAD (MLCAD)

INSTA: An Ultra-Fast, Differentiable, Statistical Static Timing Analysis Engine for Industrial Physical Design Applications

2025 ACM/IEEE Design Automation Conference (DAC)
Best Paper Award

preprint
INSTA: An Ultra-Fast, Differentiable, Statistical Static Timing Analysis Engine for Industrial Physical Design Applications

DCO-3D: Differentiable Congestion Optimization in 3D ICs

2025 ACM/IEEE Design Automation Conference (DAC)

preprint
DCO-3D: Differentiable Congestion Optimization in 3D ICs

Reinforcement Learning-Driven Window Selection for Enhanced Window-Based Rip-up and Reroute in Chip Detailed Routing

2025 ACM/IEEE Design Automation Conference (DAC)

GEM: GPU-Accelerated Emulator-Inspired RTL Simulation

2025 ACM/IEEE Design Automation Conference (DAC)

Graph Learning at Scale: Characterizing and Optimizing Pre-Propagation GNNs

2025 The Annual Conference on Machine Learning and Systems (MLSys)

ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic Interpolation

2025 ACM/IEEE Design Automation Conference (DAC)

River Segments Detection Strategy for Advanced Packages Routing

2025 IEEE VLSI-DAT

Overflow-Aware Via Placement for Dense Die-to-Die Connections in Advanced Package Routing

2025 IEEE VLSI-DAT

Hybrid Structured Clock Network Construction with GPUs for Large Designs

2025 IEEE VLSI-DAT

LEGO-Size: LLM-Enhanced GPU-Optimized Signoff-Accurate Differentiable VLSI Gate Sizing in Advanced Nodes

2025 ACM International Symposium on Physical Design (ISPD)
Nominated to Best Paper Award

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LEGO-Size: LLM-Enhanced GPU-Optimized Signoff-Accurate Differentiable VLSI Gate Sizing in Advanced Nodes

SmoothE: Differentiable E-Graph Extraction

2025 International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)

Invited: ISPD 2025 Performance-Driven Large Scale Global Routing Contest

2025 ACM International Symposium on Physical Design (ISPD)

Hybrid Exact and Heuristic Efficient Transistor Network Optimization for Multi-Output Logic

2025 ACM/IEEE Design, Automation & Test in Europe Conference (DATE)

GOALPlace: Begin with the End in Mind

2025 ACM International Symposium on Physical Design (ISPD)

DiMO-CNN: Deep Learning Toolkit-Accelerated Analytical Modeling and Optimization of CNN Hardware and Dataflow

2025 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)

Differentiable Edge-based OPC

2024 ACM/IEEE International Conference on Computer-Aided Design (ICCAD)

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Differentiable Edge-based OPC

Invited Paper: 2024 ICCAD CAD Contest Problem C: Scalable Logic Gate Sizing using ML Techniques and GPU Acceleration

2024 ACM/IEEE International Conference on Computer-Aided Design (ICCAD)

ReLS: Retrieval Is Efficient Knowledge Transfer For Logic Synthesis

2024 ACM/IEEE International Symposium on Machine Learning for CAD (MLCAD)

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ReLS: Retrieval Is Efficient Knowledge Transfer For Logic Synthesis

Learning to Compare Hardware Designs for High-Level Synthesis

2024 ACM/IEEE International Symposium on Machine Learning for CAD (MLCAD)

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Learning to Compare Hardware Designs for High-Level Synthesis

Optimizing Predictive AI in Physical Design Flows with Mini Pixel Batch Gradient Descent

ACM/IEEE International Symposium on Machine Learning for CAD

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Optimizing Predictive AI in Physical Design Flows with Mini Pixel Batch Gradient Descent

VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool

arXiv preprint

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VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool

ILILT: Implicit Learning of Inverse Lithography Technologies

International Conference on Machine Learning (ICML)

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ILILT: Implicit Learning of Inverse Lithography Technologies

Large Language Model (LLM) for Standard Cell Layout Design Optimization

The First IEEE International Workshop on LLM-Aided Design (LAD)
Best Paper Award

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Large Language Model (LLM) for Standard Cell Layout Design Optimization

Challenges for Automating PCB Layout (Invited)

2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)

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RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models

2024 ACM/IEEE Design Automation Conference (DAC)

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RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models

OpenROAD and CircuitOps: Infrastructure for ML EDA Research and Education

2024 IEEE 42nd VLSI Test Symposium

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OpenROAD and CircuitOps: Infrastructure for ML EDA Research and Education

DiMO-Sparse: Differentiable Modeling and Optimization of Sparse CNN Dataflow and Hardware Architecture

2024 Design, Automation & Test in Europe Conference (DATE)

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DiMO-Sparse: Differentiable Modeling and Optimization of Sparse CNN Dataflow and Hardware Architecture

Novel Transformer Model Based Clustering Method for Standard Cell Design Automation

2024 International Symposium on Physical Design
Best Paper Award

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Novel Transformer Model Based Clustering Method for Standard Cell Design Automation

Challenges for Automating PCB Layout (Invited)

2024 International Symposium on Physical Design

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MedPart: A Multi-Level Evolutionary Differentiable Hypergraph Partitioner

2024 ACM International Symposium on Physical Design (ISPD)

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MedPart: A Multi-Level Evolutionary Differentiable Hypergraph Partitioner

GPU/ML-Enhanced Large Scale Global Routing Contest

2024 ACM International Symposium on Physical Design (ISPD)

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GPU/ML-Enhanced Large Scale Global Routing Contest

CircuitOps: An ML Infrastructure Enabling Generative AI for VLSI Circuit Optimization

2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)

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CircuitOps: An ML Infrastructure Enabling Generative AI for VLSI Circuit Optimization

Late Breaking Results: Test Selection For RTL Coverage By Unsupervised Learning From Fast Functional Simulation

2023 Design Automation Conference (DAC)

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Late Breaking Results: Test Selection For RTL Coverage By Unsupervised Learning From Fast Functional Simulation

GATSPI: GPU accelerated gate-level simulation for power improvement

2022 Design Automation Conference (DAC)

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GATSPI: GPU accelerated gate-level simulation for power improvement

NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model

2023 International Symposium on Physical Design

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NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model

Enabling scalable AI computational lithography with physics-inspired models

Asia and South Pacific Design Automation Conference (ASP-DAC)

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Enabling scalable AI computational lithography with physics-inspired models

BufFormer: A Generative ML Framework for Scalable Buffering

2023 Asia and South Pacific Design Automation Conference (ASP-DAC)

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BufFormer: A Generative ML Framework for Scalable Buffering

Placement Optimization via PPA-Directed Graph Clustering

2022 ACM/IEEE Workshop on Machine Learning for CAD (MLCAD)
Best Paper Award

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Placement Optimization via PPA-Directed Graph Clustering

Generic lithography modeling with dual-band optics-inspired neural networks

ACM/IEEE Design Automation Conference

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Generic lithography modeling with dual-band optics-inspired neural networks

GRANNITE: Graph Neural Network Inference for Transferable Power Estimation

2020 Design Automation Conference (DAC)

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GRANNITE: Graph Neural Network Inference for Transferable Power Estimation