Virtual and augmented reality (VR/AR) are expected to revolutionise entertainment, healthcare, communication and the manufac-turing industries among many others. Near-eye displays are an enabling vessel for VR/AR applications, which have to tacklemany challenges related to ergonomics, comfort, visual quality and natural interaction. These challenges are related to thecore elements of these near-eye display hardware and tracking technologies.

We describe simple methods for how to filter environment maps using ray cones and ray differentials in a ray tracing engine.

Unlike rasterization, where one can rely on pixel quad partial derivatives, an alternative approach must be taken for filtered texturing during ray tracing. We describe two methods for computing texture level of detail for ray tracing. The first approach uses ray differentials, which is a general solution that gives high-quality results. It is rather expensive in terms of computations and ray storage, however. The second method builds on ray cone tracing and uses a single trilinear lookup, a small amount of ray storage, and fewer computations than ray differentials.

The traditional quadratic formula is often presented as the way to compute the intersection of a ray with a sphere. While mathematically correct, this factorization can be numerically unstable when using floating-point arithmetic. We give two little-known reformulations and show how each can improve precision.

We define a ray, show how to use ray intervals, and demonstrate how to specify a ray using DirectX Raytracing (DXR)

We present a technique for real-time ray tracing with the goal of reaching 240 frames per second or more. The core idea is to trade spatial resolution for faster temporal updates in such a way that the display and human visual system aid in integrating high-quality images. We use a combination of frameless and interleaved rendering concepts together with ideas from temporal antialiasing algorithms and novel building blocks---the major one being adaptive selection of pixel orderings within tiles, which reduces spatiotemporal aliasing significantly.

Modern SoCs suffer from power supply noise that can require significant additional timing margin, reducing performance and energy efficiency. Globally asynchronous, locally synchronous (GALS) systems can mitigate the impact of power supply noise, as well as simplify system design by removing the need for global timing closure. This work presents a 4mm2 distributed accelerator engine with 19 independent clock domains implemented in a 16nm process.

High-speed serial links require a very high frequency clock source. Multi-rings oscillator is a practical solution to this challenge. A new phase-interpolator embedded quadrature oscillator was designed and tested. Voltage-follower based cross-coupling loops create reliable and tunable phase relationship among OSC rings. The measurement results show that the proposed PI-OSC provides 1.25/0.97 LSB INL/DNL performance at 24GHz while consuming only 8.1mW power. This compact oscillator is suitable for clock generation in high-speed low-power links.