Dr. Angshuman Parashar joined NVIDIA in 2015 and is a member of the Architecture Research Group. His research focuses on building and evaluating architectures for spatial and data-parallel algorithms. Prior to NVIDIA, he was a member of the VSSAD group at Intel, where he worked with a small team of experts in architecture, languages, workloads and implementation to design and evaluate a new spatial architecture.

Dr. Aamer Jaleel joined NVIDIA in 2015 and is a member of the Architecture Research Group (ARG). His research work focuses on cache and DRAM systems, workload scheduling, performance modeling, and workload characterization. Prior to joining NVIDIA, he was a Principal Engineer at Intel Massachusetts Inc. in the VSSAD research group. During his decade-long career at Intel, his research work contributed towards enhancement in performance modeling and cache hierarchy improvements of Intel’s next generation microprocessors.

Bio:

Rangharajan Venkatesan is a Senior Research Scientist in the ASIC & VLSI Research group in NVIDIA. He received the B.Tech. degree in Electronics and Communication Engineering from the Indian Institute of Technology,  Roorkee in 2009 and the Ph.D. degree in Electrical and Computer Engineering from Purdue University in August 2014. His research interests include variation-tolerant design methodologies, low power SoC design, machine learning, spintronic memories, and approximate computing.

Michael Bauer joined NVIDIA Research in October of 2014 after finishing his PhD in computer science at Stanford University.  As part of his thesis, he developed the Legion programming system for high performance supercomputing codes.  Legion is currently deployed in several production applications running on the top supercomputers in the world.  Michael was also the primary author of both the CudaDMA library and Singe DSL compiler, both of which were early examples of warp-specialized GPU programming.

Dr. Joel S. Emer joined NVIDIA in 2014 and is a member of the Architecture Research group. He is also a Professor of the Practice at MIT. He is responsible for exploration of future architectures as well as modeling and analysis methodologies. Prior to joining NVIDIA he worked at Intel where he was an Intel Fellow and Director of Microarchitecture Research.  Previously he worked at Compaq and Digital Equipment Corporation.

Steven Dalton joined NVIDIA Research in July 2014. He completed his Ph.D. in computer science at UIUC, where his research focused on mapping irregular operations on sparse matrices related to algebraic multigrid (AMG) methods to GPU architectures. Along with Nathan Bell, he was one of the primary contributors to our Cusp sparse linear algebra research library. He holds two Bachelor of Science degrees from Georgia Institute of Technology in the areas of Physics and Computer Science.